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authorJohn Wickerson <>2020-11-20 09:25:20 +0000
committerJohn Wickerson <>2020-11-20 09:25:20 +0000
commitaf64bdb47eaf89fa48d211a189864d62c0fdd1eb (patch)
tree98b0d6b066ea21b0a3d3a4bfa6eb879de24ff5e9 /algorithm.tex
parentd1d33f0fcc947bf1df2a54b33f46cae25647a934 (diff)
downloadoopsla21_fvhls-af64bdb47eaf89fa48d211a189864d62c0fdd1eb.tar.gz
oopsla21_fvhls-af64bdb47eaf89fa48d211a189864d62c0fdd1eb.zip
tweaks to figure 4 (removing confusing "a" and "b" subfigures, but keeping two columns)
Diffstat (limited to 'algorithm.tex')
-rw-r--r--algorithm.tex15
1 files changed, 8 insertions, 7 deletions
diff --git a/algorithm.tex b/algorithm.tex
index 1c332d3..f8bc8ae 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -234,7 +234,7 @@ Figure~\ref{fig:accumulator_v} shows the final Verilog output that is generated
\begin{figure}
\centering
- \begin{subfigure}[b]{0.49\linewidth}
+ %\begin{subfigure}[b]{0.49\linewidth}
\begin{minted}[fontsize=\tiny]{verilog}
module main(reset, clk, finish, return_val);
reg [31:0] stack [2:0];
@@ -268,10 +268,11 @@ module main(reset, clk, finish, return_val);
default:;
endcase
\end{minted}
- \caption{Verilog always block describing the datapath of the module.}\label{fig:accumulator_v_1}
- \end{subfigure}\hfill%
- \begin{subfigure}[b]{0.49\linewidth}
-\begin{minted}[fontsize=\tiny]{verilog}
+ %\caption{Verilog always block describing the datapath of the module.}\label{fig:accumulator_v_1}
+ %\end{subfigure}\hfill%
+ %\begin{subfigure}[b]{0.49\linewidth}
+\vspace*{-63mm}
+\begin{minted}[xleftmargin=44mm, fontsize=\tiny]{verilog}
always @(posedge clk)
if ({reset == 1'd1})
state <= 32'd16;
@@ -298,8 +299,8 @@ module main(reset, clk, finish, return_val);
endcase
endmodule
\end{minted}
- \caption{Verilog always block describing the control logic of the module.}\label{fig:accumulator_v_2}
- \end{subfigure}
+ %\caption{Verilog always block describing the control logic of the module.}\label{fig:accumulator_v_2}
+ %\end{subfigure}
\caption{Accumulator example using \vericert{} to translate the 3AC to a state machine expressed in Verilog. \JW{If space permits, it would probably be preferable to have this code in a single column, as splitting a single module across two subfigures is a bit jarring.}\YH{I actually don't mind it for some reason, because it separates control flow and data path, but it's true it is weird. The only problem is it's very long if I don't do that.}}\label{fig:accumulator_v}
\end{figure}