Add C code to figure

1 files changed, 21 insertions, 8 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 7ceb0fa..b620447 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -76,7 +76,17 @@ It has an unlimited number of pseudo-registers, and is represented as a control
 \begin{figure}
   \centering
   \begin{subfigure}[b]{0.3\linewidth}
-\begin{minted}[fontsize=\footnotesize]{c}
+    \begin{subfigure}[t]{1\linewidth}
+\begin{minted}[fontsize=\footnotesize,linenos,xleftmargin=20pt]{c}
+int main() {
+    int x[1] = {3};
+    return x[0];
+}
+\end{minted}
+      \caption{Example C code passed to \vericert{}.}\label{fig:accumulator_c}
+    \end{subfigure}\\\vspace{3em}
+    \begin{subfigure}[b]{1\linewidth}
+\begin{minted}[fontsize=\footnotesize,linenos,xleftmargin=20pt]{c}
 main() {
   x2 = 3
   int32[stack(0)] = x2
@@ -84,13 +94,15 @@ main() {
   return x1
 }
 \end{minted}
-    \caption{3AC produced by \compcert{}.}\label{fig:accumulator_rtl}
+      \caption{3AC produced by \compcert{}.}\label{fig:accumulator_rtl}
+    \end{subfigure}
   \end{subfigure}\hfill%
-\begin{subfigure}[b]{0.65\linewidth}
-\vspace{1em}
-\begin{minted}[fontsize=\tiny]{verilog}
+  \begin{subfigure}[b]{0.65\linewidth}
+    \vspace{1em}
+\begin{minted}[fontsize=\tiny,linenos,xleftmargin=20pt]{verilog}
 module main(reset, clk, finish, return_val);
-  input [0:0] clk, reset; output reg [31:0] return_val = 0; output reg [0:0] finish = 0;
+  input [0:0] clk, reset; output reg [31:0] return_val = 0;
+  output reg [0:0] finish = 0;
   reg [31:0] state = 0, d_out = 0, d_in = 0, reg_1 = 0, addr = 0, reg_2 = 0;
   reg [0:0] en = 0, wr_en = 0, u_en = 0; reg [31:0] stack [0:0];
   // RAM template
@@ -104,7 +116,8 @@ module main(reset, clk, finish, return_val);
     case (state)
       32'd6: reg_1 <= d_out;
       32'd4: reg_2 <= 32'd3;
-      32'd3: begin u_en <= ( ! u_en); wr_en <= 32'd1; d_in <= reg_2; addr <= 32'd0; end
+      32'd3: begin u_en <= ( ! u_en); wr_en <= 32'd1;
+                   d_in <= reg_2; addr <= 32'd0; end
       32'd2: begin u_en <= ( ! u_en); wr_en <= 32'd0; addr <= 32'd0; end
       32'd1: begin finish <= 32'd1; return_val <= reg_1; end
       default:;
@@ -257,7 +270,7 @@ A high-level overview of the architecture can be seen in Figure~\ref{fig:accumul
 \paragraph{Translating instructions}
 
 Each 3AC instruction either corresponds to a hardware construct, or does not have to be handled by the translation, such as function calls (because of inlining).
-For example, state 15 in Figure~\ref{fig:accumulator_rtl} shows a 32-bit register \texttt{x8} being initialised to 1, after which the control flow moves to state 14. This initialisation is also encoded in HTL at state 15 in both the control- and data-path always-blocks, as shown in Figure~\ref{fig:accumulator_v}.  Simple operator instructions are translated in a similar way.  For example, in state 5, the value of the array element is added to the current sum value, which is simply translated to an addition of the equivalent registers in the HTL code.
+For example, line 2 in Figure~\ref{fig:accumulator_rtl} shows a 32-bit register \texttt{x2} being initialised to 3, after which the control flow moves execution to line 3. This initialisation is also encoded in HTL at state 4 in both the control- and data-path always-blocks, shown in Figure~\ref{fig:accumulator_v}.  Simple operator instructions are translated in a similar way.  For example, in state 5, the value of the array element is added to the current sum value, which is simply translated to an addition of the equivalent registers in the HTL code.
 
 Note that the comparison in state 3 is signed. C and Verilog handle signedness quite differently; by default, all operators and registers in Verilog (and HTL) are unsigned, so to force an operation to handle the bits as signed, both operators have to be forced to be signed.  In addition to that, Verilog implicitly resizes expressions to the largest needed size by default, which can affect the result of the computation.  This feature is not supported by the Verilog semantics we adopted, so to match the semantics to the behaviour of the simulator and synthesis tool, braces are placed around all expressions as this inhibits implicit resizing.  Instead, explicit resizing is used in the semantics and operations can only be performed on two registers that have the same size.