Fix the figures

1 files changed, 2 insertions, 1 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 2e679f2..5bde1a5 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -119,7 +119,7 @@ module main(reset, clk, finish, return_val);
     endcase
 endmodule
 \end{minted}
-\caption{Verilog produced by \vericert{}. The left column contains the data-path and the right column contains the control logic.}\label{fig:accumulator_v}
+\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM in the first always-block, the data-path in the second always-block and finally the control-logic in the last always-block.}\label{fig:accumulator_v}
 \end{subfigure}
   \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl}
 \end{figure}
@@ -243,6 +243,7 @@ Figure~\ref{fig:accumulator_diagram} shows the resulting FSMD architecture. The
 
 %\JP{Does it? Verilog has neither physical registers nor RAMs, just language constructs which the synthesiser might implement with registers and RAMs. We should be clear whether we're talking about the HDL representation, or the synthesised result: in our case these can be very different since we don't target any specific architectural features of an FPGA fabric of ASIC process.}
 \paragraph{Translating memory}
+\YH{Need to add information to this.}
 Typically, HLS-generated hardware consists of a sea of registers and RAM memories. 
 This memory view is very different to the C memory model, so we perform the following translation. 
 Variables that do not have their address taken are kept in registers, which correspond to the registers in 3AC.