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authorJohn Wickerson <j.wickerson@imperial.ac.uk>2021-04-16 09:26:35 +0000
committeroverleaf <overleaf@localhost>2021-04-16 09:27:11 +0000
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Update on Overleaf.
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@@ -150,7 +150,7 @@ module main(reset, clk, finish, return_val);
endcase
endmodule
\end{minted}
-\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the magic numbers here} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v}
+\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the magic numbers here.} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v}
\end{subfigure}
\caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl}
\end{figure}