Finish most of algorithm section

1 files changed, 21 insertions, 0 deletions

diff --git a/appendix.tex b/appendix.tex
index 2ab077e..1e3cdb3 100644
--- a/appendix.tex
+++ b/appendix.tex
@@ -5,6 +5,27 @@
 \begin{figure*}
   \centering
   \begin{minipage}{1.0\linewidth}
+    \begin{align*}
+      v\quad ::=&\; 32 \yhkeyword{'d} n\\
+      \textit{op}\quad ::=&\; \yhkeyword{+ } | \yhkeywordsp{- } | \yhkeywordsp{* } \cdots \\
+      e\quad ::=&\; v\;\; |\;\; x\;\; |\;\; e \yhkeyword{[} e \yhkeyword{]}\;\; |\;\; e\ \mathit{op}\ e\;\; |\;\; \yhkeyword{\textasciitilde} e\;\; |\;\; e \yhkeywordsp{? } e \yhkeywordsp{: } e\\
+      s\quad ::=&\; s\ s\ |\ \epsilon\\[-2pt]
+      |&\; \yhkeyword{if(} e \yhkeyword{) } s \yhkeywordsp{else } s\\[-2pt]
+      |&\; \yhkeyword{case(} e \yhkeyword{) } e : s\ \{\ e : s\ \}\ [\ s\ ] \yhkeywordsp{endcase}\\[-2pt]
+      |&\; e = e \yhkeyword{;}\\[-2pt]
+      |&\; e \Leftarrow e \yhkeyword{;}\\
+      d\quad ::=&\; \yhkeyword{[n-1:0] } r\ |\ \yhkeyword{[n-1:0] } r \yhkeywordsp{[m-1:0]}\\
+      m\quad ::=&\; \yhkeyword{reg } d \yhkeyword{;}\ |\ \yhkeyword{input wire } d \yhkeyword{;}\ |\ \yhkeyword{output reg } d \yhkeyword{;}\\
+      |&\; \yhkeywordsp{always @(posedge clk) } s \\
+      m \text{ list}\quad ::=&\; \{ m \}
+    \end{align*}
+  \end{minipage}
+  \caption{Verilog syntax for values $v$, expressions $e$, statements $s$ and module items $m$.}\label{fig:verilog_syntax}
+\end{figure*}
+
+\begin{figure*}
+  \centering
+  \begin{minipage}{1.0\linewidth}
     \begin{gather*}
       \label{eq:1}
       \inferrule[Skip]{ }{\textit{srun}\ \sigma\ \epsilon\ \sigma}\\