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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-09 20:43:47 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-09 20:43:47 +0100 |
| commit | c8f372795fa8ca90f62f556fc8cf4f17250e99ad (patch) | |
| tree | 17ebbfdb95803b0b43767e6858085073a87105e7 /archive | |
| parent | 8507d0413b34fcc2744a922048ce55ca06b7978f (diff) | |
| download | oopsla21_fvhls-c8f372795fa8ca90f62f556fc8cf4f17250e99ad.tar.gz oopsla21_fvhls-c8f372795fa8ca90f62f556fc8cf4f17250e99ad.zip | |
Fix capitalisation of titles
Diffstat (limited to 'archive')
| -rw-r--r-- | archive/verilog.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/archive/verilog.tex b/archive/verilog.tex index a363596..e4c7816 100644 --- a/archive/verilog.tex +++ b/archive/verilog.tex @@ -3,7 +3,7 @@ When targeting a hardware description language such as Verilog, it is important %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -Using these constructs it is therefore possible to describe how hardware functions, where always blocks that are triggered by a clock periodically get translated into flip-flops and always blocks triggered by changes in any internal signals are translated into combinational logic. +Using these constructs it is therefore possible to describe how hardware functions, where always-blocks that are triggered by a clock periodically get translated into flip-flops and always blocks triggered by changes in any internal signals are translated into combinational logic. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |