diff options
author | Yann Herklotz <git@yannherklotz.com> | 2020-11-02 00:27:18 +0000 |
---|---|---|
committer | Yann Herklotz <git@yannherklotz.com> | 2020-11-02 00:27:18 +0000 |
commit | 36dc41477a21e15b81b09985c9505ea1b5f10817 (patch) | |
tree | fccc68fa4f98dcf5d6b27acdf0332b3827563e5a /data | |
parent | a5561bd00606bdbbfdc014e720021d3a900b92d4 (diff) | |
download | oopsla21_fvhls-36dc41477a21e15b81b09985c9505ea1b5f10817.tar.gz oopsla21_fvhls-36dc41477a21e15b81b09985c9505ea1b5f10817.zip |
Add some more content
Diffstat (limited to 'data')
-rw-r--r-- | data/accumulator.htl | 58 | ||||
-rw-r--r-- | data/accumulator.v | 192 | ||||
-rw-r--r-- | data/accumulator_fsmd2.pdf | bin | 0 -> 28925 bytes |
3 files changed, 170 insertions, 80 deletions
diff --git a/data/accumulator.htl b/data/accumulator.htl index 16770dc..f7bdb8e 100644 --- a/data/accumulator.htl +++ b/data/accumulator.htl @@ -1,41 +1,39 @@ main() { datapath { - 16: reg_9 <= 32'd1; - 15: stack[32'd0] <= reg_9; - 14: reg_8 <= 32'd2; - 13: stack[32'd1] <= reg_8; - 12: reg_7 <= 32'd3; - 11: stack[32'd2] <= reg_7; - 10: reg_3 <= 32'd0; - 9: ; + 15: reg_8 <= 32'd1; + 14: reg_12[32'd0] <= reg_8; + 13: reg_7 <= 32'd2; + 12: reg_12[32'd1] <= reg_7; + 11: reg_6 <= 32'd3; + 10: reg_12[32'd2] <= reg_6; + 9: reg_2 <= 32'd0; 8: reg_1 <= 32'd0; - 7: reg_6 <= 32'd0; - 6: reg_5 <= stack[{{{reg_6 + 32'd0} - + {reg_1 * 32'd4}} / 32'd4}]; - 5: reg_3 <= {reg_3 + {reg_5 + 32'd0}}; + 7: reg_5 <= 32'd0; + 6: reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}]; + 5: reg_2 <= {{reg_2 + reg_4} + 32'd0}; 4: reg_1 <= {reg_1 + 32'd1}; 3: ; - 2: reg_4 <= reg_3; - 1: finish <= 1'd1; return_val <= reg_4; + 2: reg_3 <= reg_2; + 1: reg_10 = 32'd1; +reg_11 = reg_3; } controllogic { - 16: state <= 32'd15; - 15: state <= 32'd14; - 14: state <= 32'd13; - 13: state <= 32'd12; - 12: state <= 32'd11; - 11: state <= 32'd10; - 10: state <= 32'd9; - 9: state <= 32'd8; - 8: state <= 32'd7; - 7: state <= 32'd6; - 6: state <= 32'd5; - 5: state <= 32'd4; - 4: state <= 32'd3; - 3: state <= ({$signed(reg_1) < $signed(32'd3)} - ? 32'd7 : 32'd2); - 2: state <= 32'd1; + 15: reg_9 <= 32'd14; + 14: reg_9 <= 32'd13; + 13: reg_9 <= 32'd12; + 12: reg_9 <= 32'd11; + 11: reg_9 <= 32'd10; + 10: reg_9 <= 32'd9; + 9: reg_9 <= 32'd8; + 8: reg_9 <= 32'd7; + 7: reg_9 <= 32'd6; + 6: reg_9 <= 32'd5; + 5: reg_9 <= 32'd4; + 4: reg_9 <= 32'd3; + 3: reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2); + 2: reg_9 <= 32'd1; 1: ; } } + diff --git a/data/accumulator.v b/data/accumulator.v index 146176d..799756f 100644 --- a/data/accumulator.v +++ b/data/accumulator.v @@ -1,53 +1,145 @@ -module main(reset, clk, finish, return_val); - reg [31:0] stack [2:0]; - input [0:0] clk, reset; - output reg [31:0] return_val; - output reg [0:0] finish; - reg [31:0] reg_8, reg_4, state, reg_6, - reg_1, reg_9, reg_5, reg_3, reg_7; - always @(posedge clk) - case (state) - 32'd16: reg_9 <= 32'd1; - 32'd15: stack[32'd0] <= reg_9; - 32'd14: reg_8 <= 32'd2; - 32'd13: stack[32'd1] <= reg_8; - 32'd12: reg_7 <= 32'd3; - 32'd11: stack[32'd2] <= reg_7; - 32'd10: reg_3 <= 32'd0; - 32'd9: ; - 32'd8: reg_1 <= 32'd0; - 32'd7: reg_6 <= 32'd0; - 32'd6: reg_5 <= stack[{{{reg_6 + 32'd0} - + {reg_1 * 32'd4}} / 32'd4}]; - 32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}}; - 32'd4: reg_1 <= {reg_1 + 32'd1}; - 32'd3: ; - 32'd2: reg_4 <= reg_3; - 32'd1: begin finish = 1'd1; return_val = reg_4; end - default:; - endcase - always @(posedge clk) - if ({reset == 1'd1}) - state <= 32'd16; - else - case (state) - 32'd16: state <= 32'd15; - 32'd15: state <= 32'd14; - 32'd14: state <= 32'd13; - 32'd13: state <= 32'd12; - 32'd12: state <= 32'd11; - 32'd11: state <= 32'd10; - 32'd10: state <= 32'd9; - 32'd9: state <= 32'd8; - 32'd8: state <= 32'd7; - 32'd7: state <= 32'd6; - 32'd6: state <= 32'd5; - 32'd5: state <= 32'd4; - 32'd4: state <= 32'd3; - 32'd3: state <= ({$signed(reg_1) < $signed(32'd3)} - ? 32'd7 : 32'd2); - 32'd2: state <= 32'd1; - 32'd1: ; +module main(reg_13, reg_14, reg_15, reg_10, reg_11); + always @(posedge reg_15) + if ({reg_14 == 32'd1}) begin + reg_9 <= 32'd15; + end else begin + case (reg_9) + 32'd8: begin + reg_9 <= 32'd7; + end + 32'd4: begin + reg_9 <= 32'd3; + end + 32'd12: begin + reg_9 <= 32'd11; + end + 32'd2: begin + reg_9 <= 32'd1; + end + 32'd10: begin + reg_9 <= 32'd9; + end + 32'd6: begin + reg_9 <= 32'd5; + end + 32'd14: begin + reg_9 <= 32'd13; + end + 32'd1: begin + ; + end + 32'd9: begin + reg_9 <= 32'd8; + end + 32'd5: begin + reg_9 <= 32'd4; + end + 32'd13: begin + reg_9 <= 32'd12; + end + 32'd3: begin + reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2); + end + 32'd11: begin + reg_9 <= 32'd10; + end + 32'd7: begin + reg_9 <= 32'd6; + end + 32'd15: begin + reg_9 <= 32'd14; + end default:; endcase + end + always @(posedge reg_15) + case (reg_9) + 32'd8: begin + reg_1 <= 32'd0; + end + 32'd4: begin + reg_1 <= {reg_1 + 32'd1}; + end + 32'd12: begin + reg_12[32'd1] <= reg_7; + end + 32'd2: begin + reg_3 <= reg_2; + end + 32'd10: begin + reg_12[32'd2] <= reg_6; + end + 32'd6: begin + reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}]; + end + 32'd14: begin + reg_12[32'd0] <= reg_8; + end + 32'd1: begin + reg_10 = 32'd1; + reg_11 = reg_3; + end + 32'd9: begin + reg_2 <= 32'd0; + end + 32'd5: begin + reg_2 <= {{reg_2 + reg_4} + 32'd0}; + end + 32'd13: begin + reg_7 <= 32'd2; + end + 32'd3: begin + ; + end + 32'd11: begin + reg_6 <= 32'd3; + end + 32'd7: begin + reg_5 <= 32'd0; + end + 32'd15: begin + reg_8 <= 32'd1; + end + default:; + endcase + reg [31:0] reg_12 [2:0]; + reg [31:0] reg_8; + reg [31:0] reg_4; + reg [31:0] reg_2; + output reg [0:0] reg_10; + reg [31:0] reg_6; + input [0:0] reg_14; + reg [31:0] reg_1; + reg [31:0] reg_9; + reg [31:0] reg_5; + input [0:0] reg_13; + reg [31:0] reg_3; + output reg [31:0] reg_11; + reg [31:0] reg_7; + input [0:0] reg_15; +endmodule + +module testbench; + reg start, reset, clk; + wire finish; + wire [31:0] return_val; + + main m(start, reset, clk, finish, return_val); + + initial begin + clk = 0; + start = 0; + reset = 0; + @(posedge clk) reset = 1; + @(posedge clk) reset = 0; + end + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (finish == 1) begin + $display("finished: %d", return_val); + $finish; + end + end endmodule diff --git a/data/accumulator_fsmd2.pdf b/data/accumulator_fsmd2.pdf Binary files differnew file mode 100644 index 0000000..3731936 --- /dev/null +++ b/data/accumulator_fsmd2.pdf |