Add more content to algorithm

2 files changed, 64 insertions, 64 deletions

diff --git a/data/accumulator.htl b/data/accumulator.htl
index 99e3ccb..16770dc 100644
--- a/data/accumulator.htl
+++ b/data/accumulator.htl
@@ -1,41 +1,41 @@
 main() {
   datapath {
    16:	reg_9 <= 32'd1;
-   15:	reg_13[32'd0] <= reg_9;
+   15:	stack[32'd0] <= reg_9;
    14:	reg_8 <= 32'd2;
-   13:	reg_13[32'd1] <= reg_8;
+   13:	stack[32'd1] <= reg_8;
    12:	reg_7 <= 32'd3;
-   11:	reg_13[32'd2] <= reg_7;
+   11:	stack[32'd2] <= reg_7;
    10:	reg_3 <= 32'd0;
     9:	;
     8:	reg_1 <= 32'd0;
     7:	reg_6 <= 32'd0;
-    6:	reg_5 <= reg_13[{{{reg_6 + 32'd0}
+    6:	reg_5 <= stack[{{{reg_6 + 32'd0}
                         + {reg_1 * 32'd4}} / 32'd4}];
     5:	reg_3 <= {reg_3 + {reg_5 + 32'd0}};
     4:	reg_1 <= {reg_1 + 32'd1};
     3:	;
     2:	reg_4 <= reg_3;
-    1:	reg_11 <= 1'd1; reg_12 <= reg_4;
+    1:	finish <= 1'd1; return_val <= reg_4;
   }
 
   controllogic {
-   16:	reg_10 <= 32'd15;
-   15:	reg_10 <= 32'd14;
-   14:	reg_10 <= 32'd13;
-   13:	reg_10 <= 32'd12;
-   12:	reg_10 <= 32'd11;
-   11:	reg_10 <= 32'd10;
-   10:	reg_10 <= 32'd9;
-    9:	reg_10 <= 32'd8;
-    8:	reg_10 <= 32'd7;
-    7:	reg_10 <= 32'd6;
-    6:	reg_10 <= 32'd5;
-    5:	reg_10 <= 32'd4;
-    4:	reg_10 <= 32'd3;
-    3:	reg_10 <= ({$signed(reg_1) < $signed(32'd3)}
+   16:	state <= 32'd15;
+   15:	state <= 32'd14;
+   14:	state <= 32'd13;
+   13:	state <= 32'd12;
+   12:	state <= 32'd11;
+   11:	state <= 32'd10;
+   10:	state <= 32'd9;
+    9:	state <= 32'd8;
+    8:	state <= 32'd7;
+    7:	state <= 32'd6;
+    6:	state <= 32'd5;
+    5:	state <= 32'd4;
+    4:	state <= 32'd3;
+    3:	state <= ({$signed(reg_1) < $signed(32'd3)}
                         ? 32'd7 : 32'd2);
-    2:	reg_10 <= 32'd1;
+    2:	state <= 32'd1;
     1:	;
   }
 }
diff --git a/data/accumulator.v b/data/accumulator.v
index baabfe3..146176d 100644
--- a/data/accumulator.v
+++ b/data/accumulator.v
@@ -1,53 +1,53 @@
-module main(reg_14, reg_15, reg_16, reg_11, reg_12);
-  always @(posedge reg_16)
-    if ({reg_15 == 1'd1})
-      reg_10 <= 32'd16;
-    else
-      case (reg_10)
-        32'd16: reg_10 <= 32'd15;
-        32'd8: reg_10 <= 32'd7;
-        32'd4: reg_10 <= 32'd3;
-        32'd12: reg_10 <= 32'd11;
-        32'd2: reg_10 <= 32'd1;
-        32'd10: reg_10 <= 32'd9;
-        32'd6: reg_10 <= 32'd5;
-        32'd14: reg_10 <= 32'd13;
-        32'd1: ;
-        32'd9: reg_10 <= 32'd8;
-        32'd5: reg_10 <= 32'd4;
-        32'd13: reg_10 <= 32'd12;
-        32'd3: reg_10 <= ({$signed(reg_1) < $signed(32'd3)}
-                               ? 32'd7 : 32'd2);
-        32'd11: reg_10 <= 32'd10;
-        32'd7: reg_10 <= 32'd6;
-        32'd15: reg_10 <= 32'd14;
-        default:;
-      endcase
-  always @(posedge reg_16)
-    case (reg_10)
+module main(reset, clk, finish, return_val);
+  reg [31:0] stack [2:0];
+  input [0:0] clk, reset;
+  output reg [31:0] return_val;
+  output reg [0:0] finish;
+  reg [31:0] reg_8, reg_4, state, reg_6,
+             reg_1, reg_9, reg_5, reg_3, reg_7;
+  always @(posedge clk)
+    case (state)
       32'd16: reg_9 <= 32'd1;
-      32'd8: reg_1 <= 32'd0;
-      32'd4: reg_1 <= {reg_1 + 32'd1};
+      32'd15: stack[32'd0] <= reg_9;
+      32'd14: reg_8 <= 32'd2;
+      32'd13: stack[32'd1] <= reg_8;
       32'd12: reg_7 <= 32'd3;
-      32'd2: reg_4 <= reg_3;
+      32'd11: stack[32'd2] <= reg_7;
       32'd10: reg_3 <= 32'd0;
-      32'd6: reg_5 <= reg_13[{{{reg_6 + 32'd0}
-                             + {reg_1 * 32'd4}} / 32'd4}];
-      32'd14: reg_8 <= 32'd2;
-      32'd1: begin reg_11 = 1'd1; reg_12 = reg_4; end
       32'd9: ;
+      32'd8: reg_1 <= 32'd0;
+      32'd7: reg_6 <= 32'd0;
+      32'd6: reg_5 <= stack[{{{reg_6 + 32'd0}
+                           + {reg_1 * 32'd4}} / 32'd4}];
       32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}};
-      32'd13: reg_13[32'd1] <= reg_8;
+      32'd4: reg_1 <= {reg_1 + 32'd1};
       32'd3: ;
-      32'd11: reg_13[32'd2] <= reg_7;
-      32'd7: reg_6 <= 32'd0;
-      32'd15: reg_13[32'd0] <= reg_9;
+      32'd2: reg_4 <= reg_3;
+      32'd1: begin finish = 1'd1; return_val = reg_4; end
       default:;
     endcase
-  reg [31:0] reg_13 [2:0];
-  input [0:0] reg_16, reg_14, reg_15;
-  reg [31:0] reg_8, reg_4, reg_10, reg_6,
-             reg_1, reg_9, reg_5, reg_3, reg_7;
-  output reg [31:0] reg_12;
-  output reg [0:0] reg_11;
+  always @(posedge clk)
+    if ({reset == 1'd1})
+      state <= 32'd16;
+    else
+      case (state)
+        32'd16: state <= 32'd15;
+        32'd15: state <= 32'd14;
+        32'd14: state <= 32'd13;
+        32'd13: state <= 32'd12;
+        32'd12: state <= 32'd11;
+        32'd11: state <= 32'd10;
+        32'd10: state <= 32'd9;
+        32'd9: state <= 32'd8;
+        32'd8: state <= 32'd7;
+        32'd7: state <= 32'd6;
+        32'd6: state <= 32'd5;
+        32'd5: state <= 32'd4;
+        32'd4: state <= 32'd3;
+        32'd3: state <= ({$signed(reg_1) < $signed(32'd3)}
+                               ? 32'd7 : 32'd2);
+        32'd2: state <= 32'd1;
+        32'd1: ;
+        default:;
+      endcase
 endmodule