diff options
| author | n.ramanathan14 <n.ramanathan14@imperial.ac.uk> | 2020-06-25 11:42:33 +0000 |
|---|---|---|
| committer | overleaf <overleaf@localhost> | 2020-06-25 21:47:15 +0000 |
| commit | 2692815675fa33c146dc0be79ff3b4d982646e9d (patch) | |
| tree | 8d1e6707f6522eddfb24ccfdf45537de5ecb437d /evaluation.tex | |
| parent | 529762c4fa9fee0ec38b3d227bc2613ffd51a922 (diff) | |
| download | oopsla21_fvhls-2692815675fa33c146dc0be79ff3b4d982646e9d.tar.gz oopsla21_fvhls-2692815675fa33c146dc0be79ff3b4d982646e9d.zip | |
Update on Overleaf.
Diffstat (limited to 'evaluation.tex')
| -rw-r--r-- | evaluation.tex | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/evaluation.tex b/evaluation.tex new file mode 100644 index 0000000..9103942 --- /dev/null +++ b/evaluation.tex @@ -0,0 +1,32 @@ +\section{Evaluation} + +\NR{Do we want to collect C-to-Verilog compile time?} +\begin{table} +\begin{tabular}{|l|c|c|c|c|c|c|} +\hline +Benchmark & Cycles & Frequency & LUTs & Registers & BRAMs\\ +\hline\hline +adpcm & 30241 &90.05 & 7719 & 12034 & 7\\\hline +aes & 8489 & 87.83 & 24413 & 23796 & 19 \\\hline +gsm & 7190 & 119.25 & 6638 & 9201 & 3 \\\hline +mips & 7754 & 98.95 & 5049 & 4185 & 0 \\\hline +\hline +\end{tabular} +\caption{CHstone programs synthesised in LegUp 5.1} +\end{table} + +\begin{table} +\begin{tabular}{|l|c|c|c|c|c|c|} +\hline +Benchmark & Cycles & Frequency & LUTs & Registers & BRAMs\\ +\hline\hline +adpcm & XXX & XXX & XXX & XXX & XXX \\\hline +aes & 41958 & & & & \\\hline +gsm & 21994 & & & & \\\hline +mips & 18482 & 78.43 & 10617 & 7690 & 0 \\\hline +\hline +\end{tabular} +\caption{CHstone programs synthesised in CoqUp} +\end{table} + +The difference in cycle counts shows the degree of parallelism that LegUp's scheduling and memory system can offer. However, their Verilog generation is not guaranteed to be correct. Although the runtime LegUp outputs are tested to be correct for these programs, this does not provide any confidence on the correctness of Verilog generation of any other programs. Our Coq proof mechanisation guarantees that generated Verilog is correct for any input program that uses the subset of CompCert instructions that we have proven to be correct.
\ No newline at end of file |