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author | John Wickerson <j.wickerson@imperial.ac.uk> | 2020-11-20 22:32:29 +0000 |
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committer | overleaf <overleaf@localhost> | 2020-11-20 22:32:30 +0000 |
commit | 66a828209fec4c13e26116ce95d03970230036ad (patch) | |
tree | 364f73fd771a4d8d702a32970074a746bfa73c4c /evaluation.tex | |
parent | 8525a977af38b89d55142c4ea001f0e164a81e55 (diff) | |
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diff --git a/evaluation.tex b/evaluation.tex index 6c238e2..e2530ad 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -101,7 +101,7 @@ It is notable that even without \vericert{} performing many optimisations, a few %We are very encouraged by these data points. As we improve \vericert{} by incorporating further optimisations, this gap should reduce whilst preserving our correctness guarantees. -Cycle count is one factor in calculating execution times; the other is the clock frequency, which determines the duration of each of these cycles. Figure~\ref{fig:comparison_time} compares the execution times of \vericert{} and \legup{}. Across the original Polybench/C benchmarks, we see that \vericert{} designs are about $60\times$ slower than \legup{} designs. This more dramatic per +Cycle count is one factor in calculating execution times; the other is the clock frequency, which determines the duration of each of these cycles. Figure~\ref{fig:comparison_time} compares the execution times of \vericert{} and \legup{}. Across the original Polybench/C benchmarks, we see that \vericert{} designs are about $60\times$ slower than \legup{} designs. This dramatic discrepancy in performance can be largely attributed to th As mentioned earlier, we modify the Polybench programs to utilise C-based divides and modulos. We had to avoid using the built-in Verilog divides and modulos, since Quartus interprets them as single-cycle operations. This interpretation affects clock frequency drastically. On average, when using the built-in Verilog approach, \vericert{}'s clock frequency was 21MHz, compared to \legup{}'s clock frequency of 247MHz. By moving to the C-based approach, our average clock frequency is now 112MHz. Hence, we reduce the frequency gap from approximately $12\times$ to $2\times$. This gap still exists because \legup{} uses various optimisation tactics and Intel-specific IPs, which requires further engineering effort and testing from our side. |