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| author | John Wickerson <j.wickerson@imperial.ac.uk> | 2020-11-20 22:07:11 +0000 |
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| committer | overleaf <overleaf@localhost> | 2020-11-20 22:07:15 +0000 |
| commit | 768548852781106b1ac8965f183035c57e73bc9d (patch) | |
| tree | 534bee5c11e79d959a97019c96a9c6718e4bc747 /evaluation.tex | |
| parent | 1866d48e1303005462f60a629370beef28d51fe3 (diff) | |
| download | oopsla21_fvhls-768548852781106b1ac8965f183035c57e73bc9d.tar.gz oopsla21_fvhls-768548852781106b1ac8965f183035c57e73bc9d.zip | |
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diff --git a/evaluation.tex b/evaluation.tex index edb5795..09bbc70 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -19,11 +19,6 @@ We were able to use 27 of the 30 programs; three had to be discarded (\texttt{co We configured Polybench's parameters so that only integer types are used, since we do not support floats or doubles currently. We use Polybench's smallest datasets for each program to ensure that data can reside within on-chip memories of the FPGA, avoiding any need for off-chip memory accesses. - - -metadata and slightly modified the source code to suit our purposes. -First, we restrict Polybench to only generate integer data types, since we do not support floats or doubles currently. -Second, we use Polybench's smallest datasets for each program to ensure that data can reside within on-chip memories of the FPGA, avoiding any need for off-chip memory accesses. Furthermore, using the C divide or modulo operators results in directly translate to built-in Verilog divide and modulo operators. Unfortunately, the built-in operators are designed as single-cycle operation, causing large penalties in clock frequency. To work around this issue, we use a C implementation of the divide and modulo operations, which is indirectly compiles them as multi-cycle operations on the FPGA. |