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author | John Wickerson <j.wickerson@imperial.ac.uk> | 2020-11-18 16:20:14 +0000 |
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committer | overleaf <overleaf@localhost> | 2020-11-18 16:20:19 +0000 |
commit | 995cc245cb723a8445f4c1766acae312567732b0 (patch) | |
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diff --git a/introduction.tex b/introduction.tex index 9fc5771..b312fe0 100644 --- a/introduction.tex +++ b/introduction.tex @@ -43,7 +43,7 @@ The contributions of this paper are as follows: \begin{itemize} \item We present \vericert{}, the first mechanically verified HLS tool that compiles C to Verilog. The design of \vericert{} is described in Section~\ref{sec:design}. \item We prove \vericert{} correct w.r.t. an existing semantics for Verilog due to \citet{loow19_formalise}. We describe in Section~\ref{sec:verilog} how we lightly extended this semantics to make it suitable as an HLS target. Section~\ref{sec:proof} describes the proof itself. - \item We have conducted a performance comparison between \vericert{} and a widely-used (unverified) HLS tool called \legup{}~\cite{canis11_legup} using the PolyBench benchmarks. As described in Section~\ref{sec:evaluation}, \vericert{} generates hardware that is about 9x slower and 21x less area-efficient than that generated by \legup{}. We expect that these numbers will improve as we develop \vericert{} with further optimisations like loop pipelining and scheduling. + \item We have conducted a performance comparison between \vericert{} and a widely-used (unverified) HLS tool called \legup{}~\cite{canis11_legup} using the PolyBench benchmarks. As described in Section~\ref{sec:evaluation}, \vericert{} generates hardware that is about 9x slower and 21x less area-efficient than that generated by \legup{}. We expect that these numbers will improve when we extend \vericert{} with such optimisations as loop pipelining and scheduling. \end{itemize} \vericert{} is fully open source and available online. \JW{We'll have to blind this (and maybe even the name of the tool itself) for submission.} |