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authorYann Herklotz <git@yannherklotz.com>2020-06-06 19:29:34 +0100
committerYann Herklotz <git@yannherklotz.com>2020-06-06 19:29:34 +0100
commit8eb0aa72aef457d4e345f84158d828e4b2277a65 (patch)
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parent0618ca6ac08311a1325cb1860d8078ddfdb9dac0 (diff)
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@@ -190,9 +190,12 @@
%% environment and commands, and keywords command.
\maketitle
-
\section{Introduction}
+The current approach to writing energy-efficient and high-throughput applications is to use custom hardware which has been specialised for that application, instead of relying on and optimising for a CPU.\@ This comes at the cost of having to design the customised hardware, which, if using hardware description languages such as Verilog can be tedious and quite error prone. Especially with the size growing over the years, it can become difficult to verify that the hardware design behaves in the expected way, as simulation of hardware description languages can be quite inefficient. Furthermore, the algorithms that are being accelerated in hardware often already have a software implemention, meaning they have to be reimplemented efficiently in a hardware description language which can be time consuming.
+
+
+
\section{Background}
\subsection{Verilog}
@@ -277,11 +280,13 @@ based on what they evaluate to. For case I think that would end up being a three
\begin{equation}
\label{eq:9}
- \inferrule[Nonblocking]{\text{name}\ \mathit{lhs} = \mathtt{OK}\ n \\ \text{erun}\ f\ \Gamma\ \mathit{rhs}\ v_{\mathit{rhs}}}{\text{srun}\ f\ (\Gamma, \Delta)\ (\mathtt{Vnonblock}\ \mathit{lhs}\ \mathit{rhs}) = (\Gamma, \Delta ! n \rightarrow v_{\mathit{rhs}})}
+ \inferrule[Nonblocking]{\text{name}\ \mathit{lhs} = \mathtt{OK}\ n \\ \text{erun}\ f\ \Gamma\ \mathit{rhs}\ v_{\mathit{rhs}}}{\text{srun}\ f\ (\Gamma, \Delta)\ (\mathtt{Vnonblock}\ \mathit{lhs}\ \mathit{rhs}) (\Gamma, \Delta ! n \rightarrow v_{\mathit{rhs}})}
\end{equation}
\section{Proof}
+\section{Coq mechanisation}
+
\section{Conclusion}
%% Acknowledgments