Add changes

1 files changed, 10 insertions, 14 deletions

diff --git a/reviews/pldi.org b/reviews/pldi.org
index 765e7e6..2f14d3e 100644
--- a/reviews/pldi.org
+++ b/reviews/pldi.org
@@ -71,7 +71,7 @@ sound and provide a novel and proper foundation for extending to
 optimizations, so I'm giving the paper a small benefit of the doubt in
 my rating.
 
-* Other apparent weaknesses in the design
+** Other apparent weaknesses in the design
   :PROPERTIES:
   :CUSTOM_ID: other-apparent-weaknesses-in-the-design
   :END:
@@ -87,7 +87,7 @@ I can sympathize with the difficulty of getting Verilog compilers to
 identify RAMs. IMO, this is not a significant demerit of the current
 approach as part of a research prototype.
 
-* Evaluation
+** Evaluation
   :PROPERTIES:
   :CUSTOM_ID: evaluation
   :END:
@@ -103,7 +103,7 @@ coaxed into doing that kind of partial evaluation! What would be
 different in that approach, considering implementation and proof? It
 would make for another worthwhile comparison as evaluation.
 
-* Size of contribution
+** Size of contribution
   :PROPERTIES:
   :CUSTOM_ID: size-of-contribution
   :END:
@@ -119,7 +119,7 @@ It is not clear that there are strong research contributions in the
 proofs, just engineering, which seems worth doing even if there are not
 surprises in the results.
 
-* Small stuff
+** Small stuff
   :PROPERTIES:
   :CUSTOM_ID: small-stuff
   :END:
@@ -206,11 +206,7 @@ mechanically verified HLS. The tools is (somewhat) comparable to its
 (unverified-) competitor based on the aforementioned matrices, with room
 for significant improvements.
 
-** Comments for author
-   :PROPERTIES:
-   :CUSTOM_ID: comments-for-author-1
-   :END:
-* Strengths
+** Strengths
   :PROPERTIES:
   :CUSTOM_ID: strengths
   :END:
@@ -225,7 +221,7 @@ for significant improvements.
    the test candidates by preparing an alternative version of the
    benchmarks that uses repeated division and multiplications by 2.
 
-* A few Questions/Concerns
+** A few Questions/Concerns
   :PROPERTIES:
   :CUSTOM_ID: a-few-questionsconcerns
   :END:
@@ -264,7 +260,7 @@ when it is trivial to achieve that.
    should be a as challenging as certifying the instruction translation
    from C to Verilog.
 
-* nits
+** nits
   :PROPERTIES:
   :CUSTOM_ID: nits
   :END:
@@ -329,7 +325,7 @@ experience study on what was required to plug a different (formally
 verified) backend to the Compiler toolchain, a backend that caters to
 Verilog as the target language.
 
-* Strengths
+** Strengths
   :PROPERTIES:
   :CUSTOM_ID: strengths-1
   :END:
@@ -339,7 +335,7 @@ Verilog as the target language.
    studies
 3. I enjoyed studying Figure 9
 
-* Weaknesses
+** Weaknesses
   :PROPERTIES:
   :CUSTOM_ID: weaknesses
   :END:
@@ -545,7 +541,7 @@ into account new results, which this will have to count as.
 I would encourage the authors to take the feedback gathered here into
 account and resubmit with the new results to a different venue.
 
-** Response by Yann Herklotz
+* Response by Yann Herklotz
 [[mailto:yann.herklotz15@imperial.ac.uk][yann.herklotz15@imperial.ac.uk]]
    :PROPERTIES:
    :CUSTOM_ID: response-by-yann-herklotz-yann.herklotz15imperial.ac.uk