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| author | John Wickerson <j.wickerson@imperial.ac.uk> | 2020-11-17 20:44:25 +0000 |
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| committer | overleaf <overleaf@localhost> | 2020-11-17 20:44:27 +0000 |
| commit | 03649c6d6f4d4dd0c06d5ca96451757a55bafe4a (patch) | |
| tree | 0de67978ab5589616814c3ef0498c5728c864228 /verilog.tex | |
| parent | 0f5f4312e0f07edd9bf8ed4e3c44f1465454bac3 (diff) | |
| download | oopsla21_fvhls-03649c6d6f4d4dd0c06d5ca96451757a55bafe4a.tar.gz oopsla21_fvhls-03649c6d6f4d4dd0c06d5ca96451757a55bafe4a.zip | |
Update on Overleaf.
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| -rw-r--r-- | verilog.tex | 1 |
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diff --git a/verilog.tex b/verilog.tex index afea449..355b91c 100644 --- a/verilog.tex +++ b/verilog.tex @@ -14,7 +14,6 @@ A module can contain multiple always blocks, all of which run in parallel. Thes \NR{We should mention that variables cannot be driven by multiple \alwaysblock{}s, since one might get confused with data races when relating to concurrent processes in software.} - As hardware designs normally describe events that will be executed periodically for an infinite amount of time, the top-level of the semantics is best described using small-step semantics, whereas the execution of one small step is described using big-step semantics. An example of a rule in the semantics for executing an always block is shown below, where $\Sigma$ is the state of the registers in the module and $s$ is the statement inside the always block: \begin{equation*} |