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author | Yann Herklotz <git@yannherklotz.com> | 2020-06-27 19:45:57 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-27 19:45:57 +0100 |
commit | 32f043997985bea5c1df1e795bdca6d9902ba5f9 (patch) | |
tree | acab5c12ed5a0cd2064101eb37f21c36f42f04b6 /verilog.tex | |
parent | 3adbaf460ffb2531b05a55a6f38ba1654a8058c3 (diff) | |
download | oopsla21_fvhls-32f043997985bea5c1df1e795bdca6d9902ba5f9.tar.gz oopsla21_fvhls-32f043997985bea5c1df1e795bdca6d9902ba5f9.zip |
Add more semantics
Diffstat (limited to 'verilog.tex')
-rw-r--r-- | verilog.tex | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/verilog.tex b/verilog.tex index 8c1d6fa..3529866 100644 --- a/verilog.tex +++ b/verilog.tex @@ -40,6 +40,18 @@ We can then define how one step in the semantics looks like. We therefore first &\mathtt{stacksize} : n\ \big\} \end{align*} +We can then define the semantics of running the module for one clock cycle in the following way: + +\begin{gather*} + \inferrule[Module]{\Gamma_{r} ! s_{t} = \texttt{Some } v \\ (m_{i}, \Gamma_{r}^{0}, \Gamma_{a}^{0}, \epsilon, \epsilon\ l)\ \longrightarrow_{\vec{m}} (m_{i}, \Gamma_{r}^{1}, \Gamma_{a}^{1}, \Delta_{r}^{1}, \Delta_{a}^{1}) \\ (\Gamma_{r}^{1} // \Delta_{r}^{1}) ! s_{t} = \texttt{Some } v'}{\texttt{State } \textit{sf }\ m\ v\ \Gamma_{r}^{0}\ \Gamma_{a}^{0} \longrightarrow \texttt{State } \textit{sf }\ m\ v'\ (\Gamma_{r}^{1} // \Delta_{r}^{1})\ (\Gamma_{a}^{1} // \Delta_{a}^{1})}\\ +% + \inferrule[Finish]{\Gamma_{r}!\textit{fin} = \texttt{Some } 1 \\ \Gamma_{r}!\textit{ret} = \texttt{Some } r}{\texttt{State } \textit{sf }\ m\ s_{t}\ \Gamma_{r}\ \Gamma_{a} \longrightarrow \texttt{Returnstate } \textit{sf }\ r}\\ +% + \inferrule[Call]{ }{\texttt{Callstate } \textit{st }\ m\ \vec{r} \longrightarrow \texttt{State } \textit{st }\ m\ n\ (\textit{init\_params }\ \vec{r}\ a // \{s_{t} \rightarrow n\})}\\ +% + \inferrule[Return]{ }{\texttt{Returnstate } (\texttt{Stackframe } r\ m\ \textit{pc }\ \Gamma_{r}\ \Gamma_{a} :: \textit{sf}) \longrightarrow \texttt{State } \textit{sf }\ m\ \textit{pc }\ (\Gamma_{r} // \{ \textit{st} \rightarrow \textit{pc}, r \rightarrow i \})\ \epsilon} +\end{gather*} + The top level structure of a Verilog module consists of a list of module items $\vec{m}$. These are then executed sequentially while changing the associations of all the variables. We can define a function \textit{mis\_step}, which steps through all of the module items and executes them. Definition of stmntrun. |