Add verilog section

1 files changed, 1 insertions, 1 deletions

diff --git a/verilog.tex b/verilog.tex
index 7227ce8..64e1ee6 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -29,7 +29,7 @@ Two types of assignments are supported in always blocks: nonblocking and blockin
 v_{\sigma}'}{\yhconstant{State } \textit{sf }\ m\ v_{\sigma}\ \Gamma \longrightarrow \yhconstant{State } \textit{sf }\ m\ v_{\sigma}'\ (\Gamma' // \Delta')}
 \end{equation*}
 
-This rule describes how the top-level \texttt{State} used in the
+This rule describes how the top-level definition of \texttt{State} changes when one step is performed on a module $m$.
 
 When targeting a hardware description language such as Verilog, it is important to be consistent between simulating the hardware and the behaviour of the synthesised result on actual hardware.  In the target Verilog semantics, only clocked always blocks are supported as these ensure that there are not mismatches between simulation and synthesis, as combinational always blocks that trigger on any change of an internal signal may behave differently in simulation or synthesis based on the order of operations.  This limitation in the semantics therefore helps keep the Verilog correct and consistent.  In addition to that, only nonblocking assignment is used in signals that are used in multiple always blocks, which stops any race conditions from occurring as all the signal updates happen deterministically.  Finally, a specific order of evaluation for the always blocks is chosen, and because of the limitations listed before, choosing an order is guaranteed to have the same behaviour as executing the always blocks in any order.