Add city and description

1 files changed, 1 insertions, 0 deletions

diff --git a/verilog.tex b/verilog.tex
index 50d7640..1e0b9ff 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -196,6 +196,7 @@ The Verilog semantics do not define a memory model for Verilog, as this is not n
     \draw (7,-4.3) -- (12,-4.3);
     \node at (9.5,-4.7) {\small \texttt{stack[0] <= 0xDEADBEEF;}};
   \end{tikzpicture}
+  \Description{\compcert{}'s memory model is translated into a more concrete memory model based on Verilog arrays.  Two association maps are therefore needed to keep track of the blocking and nonblocking assignments.}
   \caption{Change in the memory model during the translation of 3AC into HTL.  The state of the memories in each case is right after the execution of the store to memory.}\label{fig:memory_model_transl}
 \end{figure}