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| -rw-r--r-- | algorithm.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/algorithm.tex b/algorithm.tex index 8e7f5b4..855208d 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -150,7 +150,7 @@ module main(reset, clk, finish, return_val); endcase endmodule \end{minted} -\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the abso} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} +\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the absolu} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} \end{subfigure} \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl} \end{figure} |