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| -rw-r--r-- | evaluation.tex | 58 |
1 files changed, 34 insertions, 24 deletions
diff --git a/evaluation.tex b/evaluation.tex index a946452..2a444df 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -62,12 +62,12 @@ Our evaluation is designed to answer the following three research questions. \JW table [x expr={\thisrow{legupcycles}/\thisrow{legupfreqMHz}}, y expr={\thisrow{vericertcycles}/\thisrow{vericertfreqMHz}}, col sep=comma] {results/poly.csv}; -%\addplot[dashed, domain=10:10000]{x}; -\addplot[dashed, domain=10:10000]{10*x}; +\addplot[dotted, domain=10:10000]{x}; +\addplot[dashed, domain=10:10000]{9.02*x}; \end{axis} \end{tikzpicture} -\caption{A comparison of the execution time of hardware designs generated by \vericert{} and by LegUp. The diagonal is at $y=10x$.} +\caption{A comparison of the execution time of hardware designs generated by \vericert{} and by LegUp. The diagonal is at $y=9x$.} \label{fig:comparison_time} \end{figure} @@ -85,13 +85,14 @@ The difference in cycle counts shows the degree of parallelism that \legup{}'s xlabel={LegUp (\%)}, ylabel={\vericert{} (\%)}, xmin=0, ymin=0, + xmax=1, ymax=30, ] \addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.3] table [x expr=(\thisrow{legupluts}/427200*100), y expr=(\thisrow{vericertluts}/427200*100), col sep=comma] {results/poly.csv}; - \addplot[dashed, domain=0:1]{30*x}; + %\addplot[dashed, domain=0:1]{-1.415 *x+10.6}; \end{axis} \end{tikzpicture} @@ -101,28 +102,37 @@ The difference in cycle counts shows the degree of parallelism that \legup{}'s Figure~\ref{fig:comparison_area} compares the size of the hardware designs generated by \vericert{} and by LegUp, with each data point corresponding to one of the PolyBench/C benchmarks. We see that \vericert{} designs use between 1\% and 30\% of the available logic on the FPGA, averaging at around 10\%, whereas LegUp designs all use less than 1\% of the FPGA, averaging at around 0.45\%. The main reason for this is mainly because RAM is not inferred automatically for the Verilog that is generated by \vericert{}. Other synthesis tools can infer the RAM correctly for \vericert{} output, so this issue could be solved by either using a different synthesis tool and targeting a different FPGA, or by generating the correct template which allows Quartus to identify the RAM automatically. -%\subsection{RQ3: How long does \vericert{} take to produce hardware?} -% -%\begin{figure} -%\begin{tikzpicture} -%\begin{axis}[ -% height=80mm, -% width=80mm, -% xlabel={LegUp (s)}, -% ylabel={\vericert{} (s)}, -% ] - -%\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.3] -% table [x=legupcomptime, y=vericertcomptime, col sep=comma] -% {results/comparison.csv}; +\subsection{RQ3: How long does \vericert{} take to produce hardware?} + +\begin{figure} +\begin{tikzpicture} +\begin{axis}[ + height=80mm, + width=80mm, + xlabel={LegUp (s)}, + ylabel={\vericert{} (s)}, + yticklabel style={ + /pgf/number format/fixed, + /pgf/number format/precision=2}, + xmin=4.6, + xmax=5.1, + ymin=0.06, + ymax=0.20, + ] -%\end{axis} -%\end{tikzpicture} -%\caption{A comparison of compilation time for \vericert{} and for LegUp \JW{Numbers for \vericert{} not ready yet.} \JW{This graph might end up being cut -- we might just summarise the numbers in the paragraph.}} -%\label{fig:comparison_comptime} -%\end{figure} +\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.3] + table [x=legupcomptime, y=vericertcomptime, col sep=comma] + {results/poly.csv}; + + %\addplot[dashed, domain=4.5:5.1]{0.1273*x-0.5048}; + +\end{axis} +\end{tikzpicture} +\caption{A comparison of compilation time for \vericert{} and for LegUp} +\label{fig:comparison_comptime} +\end{figure} -%Figure~\ref{fig:comparison_comptime} compares the compilation times of \vericert{} and by LegUp, with each data point corresponding to one of the PolyBench/C benchmarks. We see that \vericert{} compilation is about ten times faster than LegUp compilation. The simple reason for this is that \vericert{} omits many of the complicated and time-consuming optimisations that LegUp performs, such as scheduling multiple operations into clock cycles. +Figure~\ref{fig:comparison_comptime} compares the compilation times of \vericert{} and by LegUp, with each data point corresponding to one of the PolyBench/C benchmarks. We see that \vericert{} compilation is about ten times faster than LegUp compilation. The simple reason for this is that \vericert{} omits many of the complicated and time-consuming optimisations that LegUp performs, such as scheduling multiple operations into clock cycles. %%% Local Variables: %%% mode: latex |