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Diffstat (limited to 'algorithm.tex')
| -rw-r--r-- | algorithm.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/algorithm.tex b/algorithm.tex index 81763d7..1783c29 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -223,7 +223,7 @@ endmodule % \NR{Is the default in line 41 of (c) supposed to be empty?}\YH{Yep, that's how it's generated.} \end{figure} -\subsection{Translating C to Verilog, by Example} +\subsection{Translating C to Verilog by Example} Figure~\ref{fig:accumulator_c_rtl} illustrates the translation of a simple program that stores and retrieves values from an array. In this section, we describe the stages of the \vericert{} translation, referring to this program as an example. |