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Diffstat (limited to 'algorithm.tex')
| -rw-r--r-- | algorithm.tex | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/algorithm.tex b/algorithm.tex index 5e7868d..908f488 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -4,6 +4,7 @@ \begin{figure} \centering + \resizebox{0.47\textwidth}{!}{ \begin{tikzpicture} [language/.style={fill=white,rounded corners=2pt}] \fill[compcert,rounded corners=3pt] (-1,-1) rectangle (9,1.5); @@ -23,8 +24,9 @@ \draw[->,dashed] (ltl) -- (ppc); \draw[->] (rtl) -- (dfgstmd); \draw[->] (dfgstmd) -- (verilog); - \end{tikzpicture} - \caption{Verilog backend branching off at the RTL stage.}\label{fig:rtlbranch} + \end{tikzpicture}} + \caption{Verilog backend branching off at the RTL stage.}% + \label{fig:rtlbranch} \end{figure} This section covers the main architecture of the HLS tool, and the way in which the backend was added to CompCert. @@ -61,11 +63,11 @@ Existing HLS compilers usually use LLVM IR as an intermediate representation whe \caption{Accumulator example using CompCert to translate from HTL to Verilog.\YH{I feel like these examples take up too much space, but don't really know of a different way to show off a complete example without the long code.}}\label{fig:accumulator_htl_v} \end{figure} -\begin{figure} - \centering - \includegraphics[width=0.9\textwidth]{data/accumulator_fsmd} - \caption{Accumulator example translated to a finite state-machine with datapath (FSMD).}\label{fig:accumulator_fsmd} -\end{figure} +%\begin{figure} +% \centering +% \includegraphics[width=0.47\textwidth]{data/accumulator_fsmd} +% \caption{Accumulator example translated to a finite state-machine with datapath (FSMD).}\label{fig:accumulator_fsmd} +%\end{figure} To describe the translation, we start with an example of how to translate a simple accumulator example, which is shown in figure~\ref{fig:accumulator_c}. Using this example, the different stages of the translation can be explained, together with the way they were proven. |