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Diffstat (limited to 'evaluation.tex')
| -rw-r--r-- | evaluation.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/evaluation.tex b/evaluation.tex index ef4883e..59fc7f9 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -139,8 +139,8 @@ Cycle count is one factor in calculating execution times; the other is the clock \end{figure} Figure~\ref{fig:comparison_area} compares the resource utilisation of the Polybench programs generated by \vericert{} and \legup{}. -On average, we see that \vericert{} produces hardware that is about $21\times$ larger than \legup{}. \vericert{} designs are filling up to 30\% of a (large) FPGA chip, while $\legup$ uses no more than 1\% of the chip. -The main reason for this is mainly because RAM is not inferred automatically for the Verilog that is generated by \vericert{}; instead, large arrays of registers are synthesised instead. +On average, we see that \vericert{} produces hardware that is about $21\times$ larger than \legup{}. \vericert{} designs are filling up to 30\% of a (large) FPGA chip, while \legup{} uses no more than 1\% of the chip. +The main reason for this is that RAM is not inferred automatically for the Verilog that is generated by \vericert{}; instead, large arrays of registers are synthesised. Synthesis tools such as Quartus generally require array accesses to be in a specific form in order for RAM inference to activate. \legup{}'s Verilog generation is tailored to enable RAM inference by Quartus, while \vericert{} generates more generic array accesses. This may make \vericert{} more portable across different FPGA synthesis tools and vendors. %For a fair comparison, we chose Quartus for these experiments because LegUp supports Quartus efficiently. |