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\begin{table*}
\begin{tabular}{lcccccccccccc}
\toprule
\textbf{Benchmark} & \multicolumn{2}{c}{\bf Cycles} & \multicolumn{2}{c}{\bf Frequency / MHz} & \multicolumn{2}{c}{\bf LUTs} & \multicolumn{2}{c}{\bf Registers} & \multicolumn{2}{c}{\bf Block RAMs} & \multicolumn{2}{c}{\bf DSPs}\\
& L & V & L & V & L & V & L & V & L & V & L & V\\
\midrule
adpcm & 30241 & 121386 & 90.05 & 66.3 & 7719 & 51626 & 12034 & 42688 & 7 & 0 & 0 & 48\\
aes & 8489 & 41958 & 87.83 & 19.6 & 24413 & 104017 & 23796 & 94239 & 19 & 0 & 0 & 6\\
gsm & 7190 & 21994 & 119.25 & 66.1 & 6638 & 45764 & 9201 & 33675 & 3 & 0 & 0 & 8 \\
mips & 7754 & 18482 & 98.95 & 78.43 & 5049 & 10617 & 4185 & 7690 & 0 & 0 & 0 & 0\\
\bottomrule
\end{tabular}
\caption{CHStone programs synthesised with \legup{} 5.1 (L) and with \vericert{} (V) \JW{I guess this table is for the chop?}}\label{tab:chstone}
\end{table*}
\pgfplotstableread[col sep=comma]{results/exec-time.csv}{\nodivtimingtable}
\begin{figure}\centering
\begin{tikzpicture}
\begin{semilogyaxis}[
ybar=0pt,
width=1\textwidth,
height=0.5\textwidth,
bar width=3pt,
ymin=0.1,
ymax=3,
log ticks with fixed point,
legend pos=south east,
xlabel={Polybench Benchmarks},
xticklabels from table={\nodivtimingtable}{benchmark},
ylabel={\vericert{} / \legup{} execution time ratio},
legend style={nodes={scale=0.7, transform shape}},
x tick label style={rotate=60,anchor=east,font=\footnotesize},
xtick=data,
enlarge x limits={abs=0.5},
]
\addplot+ table [x expr=\coordindex,y=v no nc,col sep=comma] from \nodivtimingtable;
\addlegendentry{LegUp w/o opt w/o chain};
\addplot+ table [x expr=\coordindex,y=v no,col sep=comma] from \nodivtimingtable;
\addlegendentry{LegUp w/o opt};
\addplot+ table [x expr=\coordindex,y=v op,col sep=comma] from \nodivtimingtable;
\addlegendentry{LegUp};
\end{semilogyaxis}
\end{tikzpicture}
\end{figure}
\pgfplotstableread[col sep=comma]{results/slice-nodiv.csv}{\nodivslicetable}
\begin{figure}\centering
\begin{tikzpicture}
\begin{semilogyaxis}[
ybar=0pt,
width=1\textwidth,
height=0.5\textwidth,
bar width=3pt,
ymin=0.1,
ymax=3,
log ticks with fixed point,
legend pos=south east,
xlabel={Polybench Benchmarks},
xticklabels from table={\nodivslicetable}{benchmark},
ylabel={\vericert{} / \legup{} execution time ratio},
legend style={nodes={scale=0.7, transform shape}},
x tick label style={rotate=60,anchor=east,font=\footnotesize},
xtick=data,
enlarge x limits={abs=0.5},
legend columns=-1,
]
\addplot+ table [x expr=\coordindex,y=legup noopt nochain,col sep=comma] from \nodivslicetable;
\addlegendentry{LegUp w/o opt w/o chain};
\addplot+ table [x expr=\coordindex,y=legup noopt,col sep=comma] from \nodivslicetable;
\addlegendentry{LegUp w/o opt};
\addplot+ table [x expr=\coordindex,y=legup,col sep=comma] from \nodivslicetable;
\addlegendentry{LegUp};
\end{semilogyaxis}
\end{tikzpicture}
\end{figure}
\begin{figure}\centering
\begin{subfigure}[t]{0.48\textwidth}
\definecolor{cyclecountcol}{HTML}{1b9e77}
\begin{tikzpicture}
\begin{axis}[
xmode=log,
ymode=log,
height=1\textwidth,
width=1\textwidth,
xlabel={\legup{} cycle count},
ylabel={\vericert{} cycle count},
xmin=1000,
xmax=10000000,
ymax=10000000,
ymin=1000,
%log ticks with fixed point,
]
\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.6,cyclecountcol]
table [x=legupcycles, y=vericertcycles, col sep=comma]
{results/poly.csv};
\addplot[dotted, domain=1000:10000000]{x};
%\addplot[dashed, domain=10:10000]{9.02*x};
\end{axis}
\end{tikzpicture}
\caption{A comparison of the cycle count of hardware designs generated by \vericert{} and by \legup{}.}
\label{fig:comparison_cycles}
\end{subfigure}\hfill%
\begin{subfigure}[t]{0.48\textwidth}
\definecolor{polycol}{HTML}{e6ab02}
\definecolor{polywocol}{HTML}{7570b3}
\begin{tikzpicture}
\begin{axis}[
xmode=log,
ymode=log,
height=1\textwidth,
width=1\textwidth,
xlabel={\legup{} execution time (ms)},
ylabel={\vericert{} execution time (ms)},
xmin=10,
xmax=1000000,
ymax=1000000,
ymin=10,
legend pos=south east,
%log ticks with fixed point,
]
\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.8, polycol]
table [x expr={\thisrow{legupcycles}/\thisrow{legupfreqMHz}}, y expr={\thisrow{vericertcycles}/\thisrow{vericertoldfreqMHz}}, col sep=comma]
{results/poly.csv};
\addlegendentry{PolyBench}
\addplot[draw=none, mark=o, fill opacity=0, polywocol]
table [x expr={\thisrow{legupcycles}/\thisrow{legupfreqMHz}}, y expr={\thisrow{vericertcycles}/\thisrow{vericertfreqMHz}}, col sep=comma]
{results/poly.csv};
\addlegendentry{PolyBench w/o division}
\addplot[dotted, domain=10:1000000]{x};
%\addplot[dashed, domain=10:10000]{9.02*x + 442};
\end{axis}
\end{tikzpicture}
\caption{A comparison of the execution time of hardware designs generated by \vericert{} and by \legup{}.}
\label{fig:comparison_time}
\end{subfigure}
\end{figure}
\begin{figure}
\begin{subfigure}[t]{0.48\textwidth}
\definecolor{resourceutilcol}{HTML}{e7298a}
\begin{tikzpicture}
\begin{axis}[
height=1\textwidth,
width=1\textwidth,
xlabel={\legup{} resource utilisation (\%)},
ylabel={\vericert{} resource utilisation (\%)},
xmin=0, ymin=0,
xmax=1, ymax=30,
]
\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.6,resourceutilcol]
table [x expr=(\thisrow{legupluts}/427200*100), y expr=(\thisrow{vericertluts}/427200*100), col sep=comma]
{results/poly.csv};
% \addplot[dashed, domain=0:1]{x};
\end{axis}
\end{tikzpicture}
\caption{A comparison of the resource utilisation of designs generated by \vericert{} and by \legup{}.}
\label{fig:comparison_area}
\end{subfigure}\hfill%
\begin{subfigure}[t]{0.48\textwidth}
\definecolor{compiltimecol}{HTML}{66a61e}
\begin{tikzpicture}
\begin{axis}[
height=1\textwidth,
width=1\textwidth,
xlabel={\legup{} compilation time (s)},
ylabel={\vericert{} compilation time (s)},
yticklabel style={
/pgf/number format/fixed,
/pgf/number format/precision=2},
xmin=4.6,
xmax=5.1,
ymin=0.06,
ymax=0.20,
]
\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.6,compiltimecol]
table [x=legupcomptime, y=vericertcomptime, col sep=comma]
{results/poly.csv};
%\addplot[dashed, domain=4.5:5.1]{0.1273*x-0.5048};
\end{axis}
\end{tikzpicture}
\caption{A comparison of compilation time for \vericert{} and for \legup{}}
\label{fig:comparison_comptime}
\end{subfigure}
\end{figure}
%These designs therefore fill less than 1\% of the FPGA.
%The reason for the similar size in hardware is that
%Synthesis tools such as Quartus generally require array accesses to be in a specific form in order for RAM inference to activate.
%\legup{}'s Verilog generation is tailored to enable RAM inference by Quartus, while \vericert{} generates more generic array accesses. This may make \vericert{} more portable across different FPGA synthesis tools and vendors.
%%For a fair comparison, we chose Quartus for these experiments because LegUp supports Quartus efficiently.
%% Consequently, on average, \legup{} designs use $XX$ RAMs whereas \vericert{} use none.
%Enabling RAM inference is part of our future plans.
% We see that \vericert{} designs use between 1\% and 30\% of the available logic on the FPGA, averaging at around 10\%, whereas LegUp designs all use less than 1\% of the FPGA, averaging at around 0.45\%. The main reason for this is mainly because RAM is not inferred automatically for the Verilog that is generated by \vericert{}. Other synthesis tools can infer the RAM correctly for \vericert{} output, so this issue could be solved by either using a different synthesis tool and targeting a different FPGA, or by generating the correct template which allows Quartus to identify the RAM automatically.
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