1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
module main(reset, clk, finish, return_val);
input [0:0] reset, clk;
output reg [0:0] finish = 0;
output reg [31:0] return_val = 0;
reg [31:0] reg_3 = 0, addr = 0, d_in = 0, reg_5 = 0, wr_en = 0;
reg [0:0] en = 0, u_en = 0;
reg [31:0] state = 0, reg_2 = 0, reg_4 = 0, d_out = 0, reg_1 = 0;
reg [31:0] stack [1:0];
always @(negedge clk)
if ({u_en != en}) begin
if (wr_en) stack[addr] <= d_in; else d_out <= stack[addr];
en <= u_en;
end
always @(posedge clk)
case (state)
32'd11: reg_2 <= d_out;
32'd8: reg_5 <= 32'd3;
32'd7: begin u_en <= ( ! u_en); wr_en <= 32'd1;
d_in <= reg_5; addr <= 32'd0; end
32'd6: reg_4 <= 32'd6;
32'd5: begin u_en <= ( ! u_en); wr_en <= 32'd1;
d_in <= reg_4; addr <= 32'd1; end
32'd4: reg_1 <= 32'd1;
32'd3: reg_3 <= 32'd0;
32'd2: begin u_en <= ( ! u_en); wr_en <= 32'd0;
addr <= {{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}; end
32'd1: begin finish = 32'd1; return_val = reg_2; end
default: ;
endcase
always @(posedge clk)
if ({reset == 32'd1}) state <= 32'd8;
else case (state)
32'd11: state <= 32'd1;
32'd4: state <= 32'd3;
32'd8: state <= 32'd7;
32'd3: state <= 32'd2;
32'd7: state <= 32'd6;
32'd2: state <= 32'd11;
module testbench;
reg start, reset, clk;
wire finish;
wire [31:0] return_val;
reg [31:0] cycles;
main m(reset, clk, finish, return_val);
initial begin
clk = 0;
start = 0;
reset = 0;
@(posedge clk) reset = 1;
@(posedge clk) reset = 0;
cycles = 0;
end
always #5 clk = ~clk;
always @(posedge clk) begin
if (finish == 1) begin
$display("cycles: %0d", cycles);
$display("finished: %0d", return_val);
$finish;
end
cycles <= cycles + 1;
end
endmodule
|
