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module main(reg_14, reg_15, reg_16, reg_11, reg_12);
always @(posedge reg_16)
if ({reg_15 == 1'd1})
reg_10 <= 32'd16;
else
case (reg_10)
32'd16: reg_10 <= 32'd15;
32'd8: reg_10 <= 32'd7;
32'd4: reg_10 <= 32'd3;
32'd12: reg_10 <= 32'd11;
32'd2: reg_10 <= 32'd1;
32'd10: reg_10 <= 32'd9;
32'd6: reg_10 <= 32'd5;
32'd14: reg_10 <= 32'd13;
32'd1: ;
32'd9: reg_10 <= 32'd8;
32'd5: reg_10 <= 32'd4;
32'd13: reg_10 <= 32'd12;
32'd3: reg_10 <= ({$signed(reg_1) < $signed(32'd3)}
? 32'd7 : 32'd2);
32'd11: reg_10 <= 32'd10;
32'd7: reg_10 <= 32'd6;
32'd15: reg_10 <= 32'd14;
default:;
endcase
always @(posedge reg_16)
case (reg_10)
32'd16: reg_9 <= 32'd1;
32'd8: reg_1 <= 32'd0;
32'd4: reg_1 <= {reg_1 + 32'd1};
32'd12: reg_7 <= 32'd3;
32'd2: reg_4 <= reg_3;
32'd10: reg_3 <= 32'd0;
32'd6: reg_5 <= reg_13[{{{reg_6 + 32'd0}
+ {reg_1 * 32'd4}} / 32'd4}];
32'd14: reg_8 <= 32'd2;
32'd1: begin reg_11 = 1'd1; reg_12 = reg_4; end
32'd9: ;
32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}};
32'd13: reg_13[32'd1] <= reg_8;
32'd3: ;
32'd11: reg_13[32'd2] <= reg_7;
32'd7: reg_6 <= 32'd0;
32'd15: reg_13[32'd0] <= reg_9;
default:;
endcase
reg [31:0] reg_13 [2:0];
input [0:0] reg_16, reg_14, reg_15;
reg [31:0] reg_8, reg_4, reg_10, reg_6,
reg_1, reg_9, reg_5, reg_3, reg_7;
output reg [31:0] reg_12;
output reg [0:0] reg_11;
endmodule
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