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module main(reset, clk, finish, return_val);
input [0:0] clk, reset;
output reg [31:0] return_val = 0;
output reg [0:0] finish = 0;
reg [0:0] en = 0, wr_en = 0, u_en = 0;
reg [31:0] state = 0, d_out = 0, d_in = 0;
reg [31:0] reg_1 = 0, addr = 0, reg_2 = 0;
reg [31:0] stack [0:0];
always @(negedge clk)
if ({u_en != en}) begin
if (wr_en) stack[addr] <= d_in;
else d_out <= stack[addr];
en <= u_en;
end
always @(posedge clk)
case (state)
32'd6: reg_1 <= d_out;
32'd4: reg_2 <= 32'd3;
32'd3: begin
u_en <= ( ! u_en);
wr_en <= 32'd1;
d_in <= reg_2;
addr <= 32'd0;
end
32'd2: begin
u_en <= ( ! u_en);
wr_en <= 32'd0;
addr <= 32'd0;
end
32'd1: begin
finish = 32'd1;
return_val = reg_1;
end
default:;
endcase
always @(posedge clk)
if ({reset == 32'd1}) state <= 32'd4;
else case (state)
32'd6: state <= 32'd1;
32'd4: state <= 32'd3;
32'd3: state <= 32'd2;
32'd2: state <= 32'd6;
32'd1: ;
default:;
endcase
endmodule
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