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module main(start, reset, clk, finish, return_val);
reg [31:0] reg_15 = 0;
output reg [0:0] finish = 0;
input [0:0] reset;
reg [31:0] reg_3 = 0;
reg [31:0] reg_13 = 0;
reg [31:0] reg_5 = 0;
reg [0:0] reg_17 = 0;
reg [31:0] reg_1 = 0;
reg [0:0] reg_14 = 0;
reg [31:0] state = 0;
input [0:0] start;
reg [0:0] reg_18 = 0;
reg [31:0] reg_2 = 0;
input [0:0] clk;
reg [31:0] reg_4 = 0;
output reg [31:0] return_val = 0;
reg [31:0] reg_16 = 0;
reg [31:0] stack [1:0];
always @(negedge clk) begin
if ({reg_18 != reg_14}) begin
if (reg_17) begin
stack[reg_13] <= reg_15;
end else begin
reg_16 <= stack[reg_13];
end
reg_14 <= reg_18;
end else begin
;
end
end
always @(posedge clk) begin
case (state)
32'd11: begin
reg_2 <= reg_16;
end
32'd8: begin
reg_5 <= 32'd3;
end
32'd7: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd1;
reg_15 <= reg_5;
reg_13 <= 32'd0;
end
32'd6: begin
reg_4 <= 32'd6;
end
32'd5: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd1;
reg_15 <= reg_4;
reg_13 <= 32'd1;
end
32'd4: begin
reg_1 <= 32'd1;
end
32'd3: begin
reg_3 <= 32'd0;
end
32'd2: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd0;
reg_13 <= {{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4};
end
32'd1: begin
finish = 32'd1;
return_val = reg_2;
end
default:;
endcase
end
always @(posedge clk) begin
if ({reset == 32'd1}) begin
state <= 32'd8;
end else begin
case (state)
32'd11: begin
state <= 32'd1;
end
32'd8: begin
state <= 32'd7;
end
32'd7: begin
state <= 32'd6;
end
32'd6: begin
state <= 32'd5;
end
32'd5: begin
state <= 32'd4;
end
32'd4: begin
state <= 32'd3;
end
32'd3: begin
state <= 32'd2;
end
32'd2: begin
state <= 32'd11;
end
32'd1: begin
;
end
default:;
endcase
end
end
endmodule
module testbench;
reg start, reset, clk;
wire finish;
wire [31:0] return_val;
reg [31:0] cycles;
main m(start, reset, clk, finish, return_val);
initial begin
clk = 0;
start = 0;
reset = 0;
@(posedge clk) reset = 1;
@(posedge clk) reset = 0;
cycles = 0;
end
always #5 clk = ~clk;
always @(posedge clk) begin
if (finish == 1) begin
$display("cycles: %0d", cycles);
$display("finished: %0d", return_val);
$finish;
end
cycles <= cycles + 1;
end
endmodule
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