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always @(posedge clk)
if ({reset == 1'd1})
state <= 32'd16;
else
case (state)
32'd16: state <= 32'd15;
32'd15: state <= 32'd14;
32'd14: state <= 32'd13;
32'd13: state <= 32'd12;
32'd12: state <= 32'd11;
32'd11: state <= 32'd10;
32'd10: state <= 32'd9;
32'd9: state <= 32'd8;
32'd8: state <= 32'd7;
32'd7: state <= 32'd6;
32'd6: state <= 32'd5;
32'd5: state <= 32'd4;
32'd4: state <= 32'd3;
32'd3: state <=
({$signed(reg_1) < $signed(32'd3)}
? 32'd7 : 32'd2);
32'd2: state <= 32'd1;
32'd1: ;
default:;
endcase
endmodule
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