1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
module main(start, reset, clk, finish, return_val);
reg [31:0] reg_15 = 0;
output reg [0:0] finish = 0;
input [0:0] reset;
reg [31:0] reg_3 = 0;
reg [31:0] reg_13 = 0;
reg [31:0] reg_5 = 0;
reg [0:0] reg_17 = 0;
reg [31:0] reg_1 = 0;
reg [0:0] reg_14 = 0;
reg [31:0] state = 0;
input [0:0] start;
reg [0:0] reg_18 = 0;
reg [31:0] reg_2 = 0;
input [0:0] clk;
reg [31:0] reg_4 = 0;
output reg [31:0] return_val = 0;
reg [31:0] reg_16 = 0;
reg [31:0] stack [1:0];
always @(negedge clk) begin
if ({reg_18 != reg_14}) begin
if (reg_17) begin
stack[reg_13] <= reg_15;
end else begin
reg_16 <= stack[reg_13];
end
reg_14 <= reg_18;
end else begin
;
end
end
always @(posedge clk) begin
case (state)
32'd11: begin
reg_2 <= reg_16;
end
32'd8: begin
reg_5 <= 32'd3;
end
32'd7: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd1;
reg_15 <= reg_5;
reg_13 <= 32'd0;
end
32'd6: begin
reg_4 <= 32'd6;
end
32'd5: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd1;
reg_15 <= reg_4;
reg_13 <= 32'd1;
end
32'd4: begin
reg_1 <= 32'd1;
end
32'd3: begin
reg_3 <= 32'd0;
end
32'd2: begin
reg_18 <= ( ! reg_18);
reg_17 <= 32'd0;
reg_13 <= {{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4};
end
32'd1: begin
finish = 32'd1;
return_val = reg_2;
end
default:;
endcase
end
always @(posedge clk) begin
if ({reset == 32'd1}) begin
state <= 32'd8;
end else begin
case (state)
32'd11: begin
state <= 32'd1;
end
32'd8: begin
state <= 32'd7;
end
32'd7: begin
state <= 32'd6;
end
32'd6: begin
state <= 32'd5;
end
32'd5: begin
state <= 32'd4;
end
32'd4: begin
state <= 32'd3;
end
32'd3: begin
state <= 32'd2;
end
32'd2: begin
state <= 32'd11;
end
32'd1: begin
;
end
default:;
endcase
end
end
endmodule
module testbench;
reg start, reset, clk;
wire finish;
wire [31:0] return_val;
reg [31:0] cycles;
main m(start, reset, clk, finish, return_val);
initial begin
clk = 0;
start = 0;
reset = 0;
@(posedge clk) reset = 1;
@(posedge clk) reset = 0;
cycles = 0;
end
always #5 clk = ~clk;
always @(posedge clk) begin
if (finish == 1) begin
$display("cycles: %0d", cycles);
$display("finished: %0d", return_val);
$finish;
end
cycles <= cycles + 1;
end
endmodule
|