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authorYann Herklotz <git@yannherklotz.com>2022-04-17 11:22:41 +0100
committerYann Herklotz <git@yannherklotz.com>2022-04-17 11:22:41 +0100
commit2474cfa79cbb9c3afd0ca96a3ad1e0c998bf062b (patch)
tree201529d5453ca509459bc9a2676c8b24de709dd5
parent46ed5e465f59789f175d8afd2f8200526e3a5811 (diff)
downloadlsr22_fvhls-2474cfa79cbb9c3afd0ca96a3ad1e0c998bf062b.tar.gz
lsr22_fvhls-2474cfa79cbb9c3afd0ca96a3ad1e0c998bf062b.zip
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-rw-r--r--chapters/background.tex2
-rw-r--r--chapters/hls.tex46
-rw-r--r--chapters/introduction.tex35
-rw-r--r--lsr_env.tex33
-rw-r--r--main.tex9
-rw-r--r--references.bib1847
6 files changed, 71 insertions, 1901 deletions
diff --git a/chapters/background.tex b/chapters/background.tex
index 81ca653..6ca5563 100644
--- a/chapters/background.tex
+++ b/chapters/background.tex
@@ -13,7 +13,7 @@
% Catapult C~\cite{mentor20_catap_high_level_synth} & \cmark{} & \cmark{} & \cmark{} & \xmark{} & \cmark{}\\
% Chapman \textit{et al.}~\cite{chapman92_verif_bedroc} & \cmark{} & \xmark{} & \cmark{} & \cmark{} & \cmark{}\\
% Clarke \textit{et al.}~\cite{clarke03_behav_c_veril} & \cmark{} & \cmark{} & \cmark{} & \xmark{} & \cmark{}\\
-% Ellis~\cite{ellis08} & \xmark{} & \xmark{} & \cmark{} & \cmark{} & \cmark{}\\
+% Ellis~\cite{ellis08_correc} & \xmark{} & \xmark{} & \cmark{} & \cmark{} & \cmark{}\\
% Karfa \textit{et al.}~\cite{karfa06_formal_verif_method_sched_high_synth} & \cmark{} & \xmark{} & \cmark{} & \xmark{} & \cmark{}\\
% Kundu \textit{et al.}~\cite{kundu08_valid_high_level_synth} & \cmark{} & \xmark{} & \cmark{} & \xmark{} & \cmark\\
% LegUp~\cite{canis13_legup} & \cmark{} & \cmark{} & \xmark{} & \xmark{} & \cmark{}\\
diff --git a/chapters/hls.tex b/chapters/hls.tex
index 39da3b3..18227e6 100644
--- a/chapters/hls.tex
+++ b/chapters/hls.tex
@@ -9,6 +9,10 @@
\chapter[sec:hls]{High-Level Synthesis}
+This chapter outlines the base implementation of a formally verified \HLS\ tool called
+Vericert~\cite{herklotz21_veric}. This chapter is based on a paper describing the initial
+implementation in detail~\citef{herklotz21_formal_verif_high_level_synth}.
+
We have designed a new HLS tool in the Coq theorem prover and proved that any output design it
produces always has the same behaviour as its input program. Our tool, called Vericert, is
automatically extracted to an OCaml program from Coq, which ensures that the object of the proof is
@@ -39,12 +43,12 @@ function calls, non-32-bit integers, floats, and global variables.
handling of unsigned comparisons between C and Verilog, and carefully implementing memory reads
and writes so that these behave properly as a RAM in hardware.
\item In \in{Section}[sec:hls:evaluation], we evaluate Vericert on the PolyBench/C benchmark
- suite~\cite[polybench], and compare the performance of our generated hardware against an existing,
- unverified HLS tool called LegUp~\cite[canis11_legup]. We show that Vericert generates hardware
- that is \slowdownOrig$\times$ slower (\slowdownDiv$\times$ slower in the absence of division) and
- \areaIncr$\times$ larger than that generated by LegUp. This performance gap can be largely
- attributed to Vericert's current lack of support for instruction-level parallelism and the absence
- of an efficient, pipelined division operator. We intend to close this gap in the future by
+ suite~\cite[pouchet13_polyh], and compare the performance of our generated hardware against an
+ existing, unverified HLS tool called LegUp~\cite[canis11_legup]. We show that Vericert generates
+ hardware that is \slowdownOrig$\times$ slower (\slowdownDiv$\times$ slower in the absence of
+ division) and \areaIncr$\times$ larger than that generated by LegUp. This performance gap can be
+ largely attributed to Vericert's current lack of support for instruction-level parallelism and the
+ absence of an efficient, pipelined division operator. We intend to close this gap in the future by
introducing (and verifying) HLS optimisations of our own, such as scheduling and memory analysis.
This section also reports on our campaign to fuzz-test Vericert using over a hundred thousand
random C programs generated by Csmith~\cite{yang11_findin_under_bugs_c_compil} in order to confirm
@@ -60,7 +64,7 @@ function calls, non-32-bit integers, floats, and global variables.
\blank[big]
A snapshot of the Vericert development is also available in a Zenodo
-repository~\cite{yann_herklotz_2021_5093839}.
+repository~\citef{herklotz21_veric}.
\section[sec:hls:design]{Designing a Verified HLS Tool}
@@ -72,15 +76,15 @@ into hardware, expressed in the Verilog language.
\paragraph{Choice of source language.} C was chosen as the source language as it remains the most
common source language amongst production-quality HLS tools~\cite[canis11_legup,
- xilinx20_vivad_high_synth, intel_hls, bambu_hls]. This, in turn, may be because it is
-\quotation{[t]he starting point for the vast majority of algorithms to be implemented in
- hardware}~\cite{5522874}, lending a degree of practicality. The availability of
+ xilinx20_vivad_high_synth, intel20_high_synth_compil, pilato13_bambu]. This, in turn, may be
+because it is \quotation{[t]he starting point for the vast majority of algorithms to be implemented
+ in hardware}~\cite{gajski10_what_hls}, lending a degree of practicality. The availability of
CompCert~\cite{leroy09_formal_verif_realis_compil} also provides a solid basis for formally verified
C compilation. We considered Bluespec~\cite{nikhil04_blues_system_veril}, but decided that although
-it \quotation{can be classed as a high-level language}~\cite{greaves_note}, it is too hardware-oriented to
-be suitable for traditional HLS. We also considered using a language with built-in parallel
-constructs that map well to parallel hardware, such as occam~\cite{page91_compil_occam},
-Spatial~\cite{spatial} or Scala~\cite{chisel}.
+it \quotation{can be classed as a high-level language}~\cite{greaves19_resear_note}, it is too
+hardware-oriented to be suitable for traditional HLS. We also considered using a language with
+built-in parallel constructs that map well to parallel hardware, such as
+occam~\cite{page91_compil_occam}, Spatial~\cite{spatial} or Scala~\cite{bachrach12_chisel}.
\paragraph{Choice of target language.} Verilog~\cite{06_ieee_stand_veril_hardw_descr_languag} is an
HDL that can be synthesised into logic cells which can either be placed onto a field-programmable
@@ -102,9 +106,9 @@ validated C parser~\cite{jourdan12_valid_lr_parser}. The Vellvm
framework~\cite{zhao12_formal_llvm_inter_repres_verif_progr_trans} was also considered because
several existing HLS tools are already LLVM-based, but additional work would be required to support
a high-level language like C as input. The .NET framework has been used as a basis for other HLS
-tools, such as Kiwi~\cite{kiwi}, and LLHD~\cite{schuiki20_llhd} has been recently proposed as an
-intermediate language for hardware design, but neither are suitable for us because they lack formal
-semantics.
+tools, such as Kiwi~\cite{greaves08_kiwi}, and LLHD~\cite{schuiki20_llhd} has been recently proposed
+as an intermediate language for hardware design, but neither are suitable for us because they lack
+formal semantics.
\startplacefigure[title={Vericert as a Verilog back end to CompCert.}]
\hbox{\starttikzpicture [language/.style={fill=white,rounded corners=3pt,minimum height=7mm},
@@ -164,10 +168,10 @@ We select CompCert's three-address code (3AC)\footnote{This is known as register
tool.} as the starting point. Branching off \emph{before} this point (at CminorSel or earlier)
denies CompCert the opportunity to perform optimisations such as constant propagation and dead-code
elimination, which, despite being designed for software compilers, have been found useful in HLS
-tools as well~\cite{cong+11}. And if we branch off \emph{after} this point (at LTL or later) then
-CompCert has already performed register allocation to reduce the number of registers and spill some
-variables to the stack; this transformation is not required in HLS because there are many more
-registers available, and these should be used instead of RAM whenever possible.
+tools as well~\cite{cong11_high_level_synth_fpgas}. And if we branch off \emph{after} this point (at
+LTL or later) then CompCert has already performed register allocation to reduce the number of
+registers and spill some variables to the stack; this transformation is not required in HLS because
+there are many more registers available, and these should be used instead of RAM whenever possible.
3AC is also attractive because it is the closest intermediate language to LLVM IR, which is used by
several existing HLS compilers. It has an unlimited number of pseudo-registers, and is represented
diff --git a/chapters/introduction.tex b/chapters/introduction.tex
index d96ff55..8588d3f 100644
--- a/chapters/introduction.tex
+++ b/chapters/introduction.tex
@@ -3,21 +3,28 @@
\chapter{Introduction}
\startthesis
-An optimising high-level synthesis tool can be proven correct using an interactive theorem prover
-while also remaining practical.
+ An optimising \infull{HLS} tool can be proven correct using an interactive theorem prover while
+ also remaining practical.
\stopthesis
\noindent As latency, throughput, and energy efficiency become increasingly important, custom
hardware accelerators are being designed for numerous applications. Alas, designing these
accelerators can be a tedious and error-prone process using a hardware description language (HDL)
-such as Verilog. An attractive alternative is \emph{high-level synthesis} (HLS), in which hardware
-designs are automatically compiled from software written in a high-level language like C. Modern
-HLS tools such as LegUp~\cite{canis11_legup}, Vivado HLS~\cite{xilinx20_vivad_high_synth}, Intel
-i++~\cite{intel_hls}, and Bambu HLS~\cite{bambu_hls} promise designs with comparable performance and
-energy-efficiency to those hand-written in an HDL~\cite{homsirikamol+14, silexicahlshdl, 7818341},
-while offering the convenient abstractions and rich ecosystems of software development. But
-existing HLS tools cannot always guarantee that the hardware designs they produce are equivalent to
-the software they were given, and this undermines any reasoning conducted at the software level.
+such as Verilog. An attractive alternative is \emph{\infull{HLS}} (\HLS), in which hardware designs
+are automatically compiled from software written in a high-level language like C. Modern \HLS\
+tools such as LegUp~\cite{canis11_legup}, Vivado HLS~\cite{xilinx20_vivad_high_synth}, Intel
+i++~\cite{intel20_high_synth_compil}, and Bambu HLS~\cite{pilato13_bambu} promise designs with
+comparable performance and energy-efficiency to those hand-written in an
+HDL~\cite{homsirikamol14_can, gauthier20_high_level_synth, pelcat16_desig_hdl}, while offering the
+convenient abstractions and rich ecosystems of software development.
+
+There are two main use-cases of \HLS. Firstly, it is a very convenient tool to use for prototyping
+designs, as this means that the software model can be reused for the initial design of the hardware.
+Secondly, \HLS\ is also often used design hardware that has quite regular control-flow and is
+compute intensive, one example being DSP hardware design.
+
+But existing HLS tools cannot always guarantee that the hardware designs they produce are equivalent
+to the software they were given, and this undermines any reasoning conducted at the software level.
Indeed, there are reasons to doubt that HLS tools actually \emph{do} always preserve equivalence.
For instance, Vivado HLS has been shown to apply pipelining optimisations
@@ -27,7 +34,7 @@ supports.\footnote{\goto{bit.ly/vivado-hls-pointer-bug}[url(https://bit.ly/vivad
Meanwhile, \cite{lidbury15_many_core_compil_fuzzin} had to abandon their attempt to fuzz-test
Altera's (now Intel's) OpenCL compiler since it \quotation{either crashed or emitted an internal
compiler error} on so many of their test inputs. More recently,
-\cite{herklotz21_empir_study_reliab_high_level_synth_tools} fuzz-tested three commercial HLS tools
+\citef{herklotz21_empir_study_reliab_high_level_synth_tools} fuzz-tested three commercial HLS tools
using Csmith~\cite{yang11_findin_under_bugs_c_compil}, and despite restricting the generated
programs to the C fragment explicitly supported by all the tools, they still found that on average
2.5\% of test-cases were compiled to designs that behaved incorrectly.
@@ -44,9 +51,9 @@ optimisations~\cite{kim04_autom_fsmd,karfa06_formal_verif_method_sched_high_synt
Nevertheless, it is an expensive task, especially for large designs, and it must be repeated every
time the compiler is invoked. For example, the translation validation for Catapult
C~\cite{mentor20_catap_high_level_synth} may require several rounds of expert
-`adjustments'~\cite[alternative=authoryear,right={, p.~3)}][slec_whitepaper] to the input C program
-before validation succeeds. And even when it succeeds, translation validation does not provide
-watertight guarantees unless the validator itself has been mechanically proven
+`adjustments'~\cite[alternative=authoryear,right={, p.~3)}][chauhan20_formal_ensur_equiv_c_rtl] to
+the input C program before validation succeeds. And even when it succeeds, translation validation
+does not provide watertight guarantees unless the validator itself has been mechanically proven
correct~\cite[tristan08_formal_verif_trans_valid], which has not been the case in HLS tools to date.
Our position is that none of the above workarounds are necessary if the HLS tool can simply be
diff --git a/lsr_env.tex b/lsr_env.tex
index 78bf572..86984e3 100644
--- a/lsr_env.tex
+++ b/lsr_env.tex
@@ -32,6 +32,8 @@
\setupalign[hz,hanging]
\setuptolerance[stretch,tolerant]
+\setuppagenumbering[location=none]
+
\setuplayout[
edgedistance=1cm,
backspace=2cm,
@@ -60,25 +62,32 @@
]
\startsectionblockenvironment [backpart]
-\setuppagenumbering[location={footer,middle}]
+
+\setuplayout[wide]
\setupheads[chapter][
- after=,
- before=,
+ after={\blank[2*big]},
+ before={\blank[big,force]},
style={\bfd},
header=empty,
align=flushleft,
]
+
+\setupfootertexts[pagenumber]
+
\stopsectionblockenvironment
\startsectionblockenvironment [frontpart]
-\setuppagenumbering[location={footer,middle}]
+\setuplayout[wide]
\setupheads[chapter][
- after=,
- before=,
+ after={\blank[2*big]},
+ before={\blank[big,force]},
style={\bfd},
header=empty,
align=flushleft,
]
+
+\setupfootertexts[pagenumber]
+
\stopsectionblockenvironment
% @see http://wiki.contextgarden.net/Command/setuppagenumbering
@@ -134,10 +143,7 @@
\setuphead[subsection][style={\bfa}]
\setuphead[subsubsection][style={\bf},after={\blank[0.2cm]}]
-\setuppagenumbering[location=]
\setuplabeltext[chapter=]
-\setupheadertexts[margin][][{{\it \getmarking[chapter]}\wordright{\pagenumber}}]
-\setupheadertexts[text][][{\someheadnumber[chapter][current]}]
% \setupheader[text][style=smallcaps,after=\hrule]
% \setupheader[margin][style=smallcaps]
@@ -152,6 +158,11 @@
%]
\startsectionblockenvironment [bodypart]
+\setuplayout[reset]
+
+\setupheadertexts[margin][][{{\it \getmarking[chapter]}\wordright{\pagenumber}}]
+\setupheadertexts[text][][{\someheadnumber[chapter][current]}]
+
\setcounter[userpage][1]
\stopsectionblockenvironment
@@ -265,7 +276,7 @@
% \usebtxdefinitions[apa]
% \setupbtx[default:cite][alternative=authoryear]
% @see https://tex.stackexchange.com/a/294571
-\usebtxdataset[references]
+\usebtxdataset[bibliography]
\usebtxdefinitions[apa]
\setupbtx[default:cite][alternative=authoryear]
@@ -345,6 +356,8 @@
\abbreviation{SAT}{satisfiability}
\abbreviation{SMT}{satisfiability modulo scheduling}
+\define[1]\citef{\cite[#1]\footnote{\cite[entry][#1]}}
+
\usemodule[gantt-s-tikz]
\setupenumerations
diff --git a/main.tex b/main.tex
index b7e5c00..c9ee69b 100644
--- a/main.tex
+++ b/main.tex
@@ -7,27 +7,21 @@
\mainlanguage[en]
-% Common module shared by all.
-% @see http://wiki.contextgarden.net/Dummy_text
-% \usemodule[visual]
-
% \showlayout
% \showsetups
% \showgrid
% \showmakeup
-\showframe
+% \showframe
% \showbodyfontenvironment
%\showbodyfont
\component title
\startfrontmatter
- \setuplayout[wide]
\completecontent
\stopfrontmatter
\startbodymatter
- \setuplayout[reset]
\component introduction
\component background
\component hls
@@ -39,7 +33,6 @@
\stopbodymatter
\startbackmatter
- \setuplayout[wide]
\chapter{Bibliography}
\placelistofpublications
\stopbackmatter
diff --git a/references.bib b/references.bib
deleted file mode 100644
index 8dd4b3b..0000000
--- a/references.bib
+++ /dev/null
@@ -1,1847 +0,0 @@
-@article{leroy09_formal_verif_realis_compil,
- author = {Leroy, Xavier},
- title = {Formal Verification of a Realistic Compiler},
- journal = {Commun. ACM},
- volume = 52,
- number = 7,
- pages = {107-115},
- year = 2009,
- doi = {10.1145/1538788.1538814},
- address = {New York, NY, USA},
- issn = {0001-0782},
- issue_date = {July 2009},
- month = jul,
- numpages = 9,
- publisher = {ACM},
-}
-
-@article{six+20,
- author={Cyril Six and Sylvain Boulm\'e and David Monniaux},
- title = {{Certified and efficient instruction scheduling: Application to interlocked {VLIW} processors}},
- journal = {Proc. {ACM} Program. Lang.},
- number = {{OOPSLA}},
- year = {2020}
- }
-
-@inproceedings{lidbury15_many_core_compil_fuzzin,
- author = {Lidbury, Christopher and Lascu, Andrei and Chong, Nathan and Donaldson,
- Alastair F.},
- title = {Many-Core Compiler Fuzzing},
- booktitle = {Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design
- and Implementation},
- year = 2015,
- pages = {65-76},
- doi = {10.1145/2737924.2737986},
- address = {New York, NY, USA},
- isbn = 9781450334686,
- location = {Portland, OR, USA},
- numpages = 12,
- publisher = {ACM},
- series = {PLDI '15},
-}
-
-@misc{polybench,
-author = {Pouchet, Louis-No\"el},
-title = {PolyBench/C: the Polyhedral Benchmark suite},
-url = {http://web.cse.ohio-state.edu/~pouchet.2/software/polybench/},
-year = {2020},
-}
-
-@INPROCEEDINGS{5522874,
- author={Dan Gajski and Todd Austin and Steve Svoboda},
- booktitle={Design Automation Conference},
- title={What input-language is the best choice for high level synthesis (HLS)?},
- year={2010},
- volume={},
- number={},
- pages={857-858},
- doi={10.1145/1837274.1837489}}
-
-@inproceedings{bluespec,
- author={Nikhil, Rishiyur S. },
- booktitle={Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04.},
- title={Bluespec System Verilog: efficient, correct RTL from high level specifications},
- year={2004},
- volume={},
- number={},
- pages={69-70},
- doi={10.1109/MEMCOD.2004.1459818}}
-
-@inproceedings{davidthomas_asap16,
- author = {Thomas, David B.},
- title = {Synthesisable recursion for {C++} {HLS} tools},
- booktitle = {{ASAP}},
- pages = {91--98},
- publisher = {{IEEE} Computer Society},
- year = {2016},
- doi = {10.1109/ASAP.2016.7760777}
-}
-
-@article{cong+11,
- author = {Jason Cong and
- Bin Liu and
- Stephen Neuendorffer and
- Juanjo Noguera and
- Kees A. Vissers and
- Zhiru Zhang},
- title = {High-Level Synthesis for FPGAs: From Prototyping to Deployment},
- journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
- volume = {30},
- number = {4},
- pages = {473--491},
- year = {2011},
- doi = {10.1109/TCAD.2011.2110592}
-}
-
-@inproceedings{kiwi,
- author = {David J. Greaves and
- Satnam Singh},
- title = {Kiwi: Synthesis of {FPGA} Circuits from Parallel Programs},
- booktitle = {{FCCM}},
- pages = {3--12},
- publisher = {{IEEE} Computer Society},
- year = {2008},
- doi={10.1109/FCCM.2008.46}
-}
-
-@inproceedings{spatial,
- author = {David Koeplinger and
- Matthew Feldman and
- Raghu Prabhakar and
- Yaqi Zhang and
- Stefan Hadjis and
- Ruben Fiszel and
- Tian Zhao and
- Luigi Nardi and
- Ardavan Pedram and
- Christos Kozyrakis and
- Kunle Olukotun},
- title = {Spatial: A Language and Compiler for Application Accelerators},
- booktitle = {{PLDI}},
- pages = {296--311},
- publisher = {{ACM}},
- year = {2018},
- doi = {https://doi.org/10.1145/3192366.3192379}
-}
-
-@misc{greaves_note,
- title={Research Note: An Open Source Bluespec Compiler},
- author={David J. Greaves},
- year={2019},
- eprint={1905.03746},
- archivePrefix={arXiv},
- primaryClass={cs.PL}
-}
-
-@article{takach16_high_level_synth,
- author = {A. {Takach}},
- title = {High-Level Synthesis: Status, Trends, and Future
- Directions},
- journal = {IEEE Design Test},
- volume = {33},
- number = {3},
- pages = {116-124},
- year = {2016},
- doi = {10.1109/MDAT.2016.2544850},
- url = {https://doi.org/10.1109/MDAT.2016.2544850},
- ISSN = {2168-2364},
- month = {June},
-}
-
-@inproceedings{liu16_effic_high_level_synth_desig,
- author = { {Dong Liu} and B. C. {Schafer}},
- title = {Efficient and reliable High-Level Synthesis Design Space
- Explorer for FPGAs},
- booktitle = {2016 26th International Conference on Field Programmable
- Logic and Applications (FPL)},
- year = 2016,
- pages = {1-8},
- doi = {10.1109/FPL.2016.7577370},
- ISSN = {1946-1488},
- month = {Aug},
-}
-
-@article{lahti19_are_we_there_yet,
- author = {S. {Lahti} and P. {Sj{\"o}vall} and J. {Vanne} and
- T. D. {H{\"a}m{\"a}l{\"a}inen}},
- title = {Are We There Yet? a Study on the State of High-Level
- Synthesis},
- journal = {IEEE Transactions on Computer-Aided Design of Integrated
- Circuits and Systems},
- volume = {38},
- number = {5},
- pages = {898-911},
- year = {2019},
- doi = {10.1109/TCAD.2018.2834439},
- ISSN = {1937-4151},
- month = {May},
-}
-
-@misc{mentor20_catap_high_level_synth,
- author = {Mentor},
- title = {Catapult High-Level Synthesis},
- url = {https://www.mentor.com/hls-lp/catapult-high-level-synthesis/c-systemc-hls},
- urldate = {2020-06-06},
- year = 2020,
-}
-
-@inproceedings{gupta03_spark,
- author = {{Gupta}, S. and {Dutt}, N. and {Gupta}, R. and {Nicolau}, A.},
- title = {{SPARK}: a high-level synthesis framework for applying parallelizing compiler
- transformations},
- booktitle = {16th International Conference on VLSI Design, 2003. Proceedings.},
- year = 2003,
- pages = {461-466},
- doi = {10.1109/ICVD.2003.1183177},
- url = {https://doi.org/10.1109/ICVD.2003.1183177},
- ISSN = {1063-9667},
- month = {Jan},
-}
-
-@article{chouksey20_verif_sched_condit_behav_high_level_synth,
- author = {Chouksey, R. and Karfa, C.},
- title = {Verification of Scheduling of Conditional Behaviors in
- High-Level Synthesis},
- journal = {IEEE Transactions on Very Large Scale Integration (VLSI)
- Systems},
- volume = {},
- number = {},
- pages = {1-14},
- year = {2020},
- doi = {10.1109/TVLSI.2020.2978242},
- url = {https://doi.org/10.1109/TVLSI.2020.2978242},
- ISSN = {1557-9999},
- month = {},
-}
-
-@inproceedings{pnueli98_trans,
- author = "Pnueli, A. and Siegel, M. and Singerman, E.",
- title = "Translation validation",
- booktitle = "Tools and Algorithms for the Construction and Analysis of Systems",
- year = 1998,
- pages = "151--166",
- address = "Berlin, Heidelberg",
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- booktitle={DAC Design Automation Conference 2012},
- pages={1212--1221},
- year={2012},
- organization={IEEE},
- doi={https://doi.org/10.1145/2228360.2228584},
-}
-
-@article{aubury1996handel,
- title={Handel-C language reference guide},
- author={Aubury, Matthew and Page, Ian and Randall, Geoff and Saul, Jonathan and Watts, Robin},
- journal={Computing Laboratory. Oxford University, UK},
- year={1996}
-}
-
-@inproceedings{clarke03_behav_c_veril,
- author = {E. {Clarke} and D. {Kroening} and K. {Yorav}},
- title = {Behavioral consistency of {C} and {Verilog} programs using bounded model checking},
- booktitle = {Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)},
- year = 2003,
- pages = {368-371},
- doi = {10.1145/775832.775928},
- url = {https://doi.org/10.1145/775832.775928},
-}
-
-@article{besson18_compc,
- doi = {10.1007/s10817-018-9496-y},
- url = {https://doi.org/10.1007/s10817-018-9496-y},
- year = {2018},
- month = nov,
- publisher = {Springer Science and Business Media {LLC}},
- volume = {63},
- number = {2},
- pages = {369--392},
- author = {Fr{\'{e}}d{\'{e}}ric Besson and Sandrine Blazy and Pierre Wilke},
- title = {{CompCertS}: A Memory-Aware Verified C Compiler Using a Pointer as Integer Semantics},
- journal = {Journal of Automated Reasoning}
-}
-
-@article{sevcik13_compc,
- author = {\v{S}ev\v{c}\'{\i}k, Jaroslav and Vafeiadis, Viktor and Zappa Nardelli, Francesco and Jagannathan, Suresh and Sewell, Peter},
- title = {CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency},
- year = {2013},
- issue_date = {June 2013},
- publisher = {ACM},
- address = {New York, NY, USA},
- volume = {60},
- number = {3},
- issn = {0004-5411},
- url = {https://doi.org/10.1145/2487241.2487248},
- doi = {10.1145/2487241.2487248},
- abstract = {In this article, we consider the semantic design and verified compilation of a C-like programming language for concurrent shared-memory computation on x86 multiprocessors. The design of such a language is made surprisingly subtle by several factors: the relaxed-memory behavior of the hardware, the effects of compiler optimization on concurrent code, the need to support high-performance concurrent algorithms, and the desire for a reasonably simple programming model. In turn, this complexity makes verified compilation both essential and challenging.We describe ClightTSO, a concurrent extension of CompCert’s Clight in which the TSO-based memory model of x86 multiprocessors is exposed for high-performance code, and CompCertTSO, a formally verified compiler from ClightTSO to x86 assembly language, building on CompCert. CompCertTSO is verified in Coq: for any well-behaved and successfully compiled ClightTSO source program, any permitted observable behavior of the generated assembly code (if it does not run out of memory) is also possible in the source semantics. We also describe some verified fence-elimination optimizations, integrated into CompCertTSO.},
- journal = {J. ACM},
- month = jun,
- articleno = {22},
- numpages = {50},
- keywords = {semantics, Relaxed memory models, verified compilation}
-}
-
-@article{wang20_compc,
- author = {Wang, Yuting and Xu, Xiangzhe and Wilke, Pierre and Shao, Zhong},
- title = {CompCertELF: Verified Separate Compilation of C Programs into ELF Object Files},
- year = {2020},
- issue_date = {November 2020},
- publisher = {ACM},
- address = {New York, NY, USA},
- volume = {4},
- number = {OOPSLA},
- url = {https://doi.org/10.1145/3428265},
- doi = {10.1145/3428265},
- abstract = { We present CompCertELF, the first extension to CompCert that supports verified compilation from C programs all the way to a standard binary file format, i.e., the ELF object format. Previous work on Stack-Aware CompCert provides a verified compilation chain from C programs to assembly programs with a realistic machine memory model. We build CompCertELF by modifying and extending this compilation chain with a verified assembler which further transforms assembly programs into ELF object files. CompCert supports large-scale verification via verified separate compilation: C modules can be written and compiled separately, and then linked together to get a target program that refines the semantics of the program linked from the source modules. However, verified separate compilation in CompCert only works for compilation to assembly programs, not to object files. For the latter, the main difficulty is to bridge the two different views of linking: one for CompCert's programs that allows arbitrary shuffling of global definitions by linking and the other for object files that treats blocks of encoded definitions as indivisible units. We propose a lightweight approach that solves the above problem without any modification to CompCert's framework for verified separate compilation: by introducing a notion of syntactical equivalence between programs and proving the commutativity between syntactical equivalence and the two different kinds of linking, we are able to transit from the more abstract linking operation in CompCert to the more concrete one for ELF object files. By applying this approach to CompCertELF, we obtain the first compiler that supports verified separate compilation of C programs into ELF object files. },
- journal = {Proc. ACM Program. Lang.},
- month = nov,
- articleno = {197},
- numpages = {28},
- keywords = {Generation of Object Files, Assembler Verification, Verified Separate Compilation}
-}
-
-@inproceedings{10.1145/3437992.3439916,
-author = {L\"{o}\"{o}w, Andreas},
-title = {Lutsig: A Verified Verilog Compiler for Verified Circuit Development},
-year = {2021},
-isbn = {9781450382991},
-publisher = {ACM},
-address = {New York, NY, USA},
-url = {https://doi.org/10.1145/3437992.3439916},
-doi = {10.1145/3437992.3439916},
-abstract = {We report on a new verified Verilog compiler called Lutsig. Lutsig currently targets (a class of) FPGAs and is capable of producing technology mapped netlists for FPGAs. We have connected Lutsig to existing Verilog development tools, and in this paper we show how Lutsig, as a consequence of this connection, fits into a hardware development methodology for verified circuits in the HOL4 theorem prover. One important step in the methodology is transporting properties proved at the behavioral Verilog level down to technology mapped netlists, and Lutsig is the component in the methodology that enables such transportation.},
-booktitle = {Proceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs},
-pages = {46–60},
-numpages = {15},
-keywords = {hardware verification, hardware synthesis, compiler verification},
-location = {Virtual, Denmark},
-series = {CPP 2021}
-}
-
-@inproceedings{paulin89_sched_bindin_algor_high_level_synth,
- author = {Paulin, P. G. and Knight, J. P.},
- title = {Scheduling and Binding Algorithms for High-Level Synthesis},
- booktitle = {Proceedings of the 26th ACM/IEEE Design Automation Conference},
- year = 1989,
- pages = {1-6},
- doi = {10.1145/74382.74383},
- url = {https://doi.org/10.1145/74382.74383},
- address = {New York, NY, USA},
- isbn = 0897913108,
- location = {Las Vegas, Nevada, USA},
- numpages = 6,
- publisher = {ACM},
- series = {DAC '89},
-}
-
-@inproceedings{venkataramani07_operat,
- keywords = {operation chaining},
- author = {Girish Venkataramani and Goldstein, Seth C.},
- booktitle = {2007 IEEE/ACM International Conference on Computer-Aided Design},
- title = {Operation chaining asynchronous pipelined circuits},
- year = {2007},
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- pages = {442-449},
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-@inproceedings{noronha17_rapid_fpga,
- keywords = {high-level synthesis, FPGA, inlining, compiler optimisation},
- author = {{Noronha}, D. H. and {Pinilla}, J. P. and {Wilton}, S. J. E.},
- booktitle = {2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
- title = {Rapid circuit-specific inlining tuning for FPGA high-level synthesis},
- year = {2017},
- volume = {},
- number = {},
- pages = {1-6},
- doi = {10.1109/RECONFIG.2017.8279807}
-}
-
-@misc{yann_herklotz_2021_5093839,
- author = {Yann Herklotz and
- James D. Pollard and
- Nadesh Ramanathan and
- John Wickerson},
- title = {Vericert v1.2.1},
- month = jul,
- year = 2021,
- publisher = {Zenodo},
- version = {v1.2.1},
- doi = {10.5281/zenodo.5093839},
- url = {https://doi.org/10.5281/zenodo.5093839}
-}
-
-@INPROCEEDINGS{herklotz21_empir_study_reliab_high_level_synth_tools,
- author = {Herklotz, Yann and Du, Zewei and Ramanathan, Nadesh and Wickerson, John},
- booktitle = {2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
- title = {An Empirical Study of the Reliability of High-Level Synthesis Tools},
- year = {2021},
- volume = {},
- number = {},
- pages = {219-223},
- doi = {10.1109/FCCM51124.2021.00034}
-}
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- author = {Leroy, Xavier},
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- numpages = 9,
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-@inproceedings{lidbury15_many_core_compil_fuzzin,
- author = {Lidbury, C. and Lascu, A. and Chong, N. and Donaldson, A. F.},
- title = {Many-Core Compiler Fuzzing},
- booktitle = {Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design
- and Implementation},
- year = 2015,
- pages = {65-76},
- doi = {10.1145/2737924.2737986},
- address = {New York, NY, USA},
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- location = {Portland, OR, USA},
- numpages = 12,
- publisher = {Association for Computing Machinery},
- series = {PLDI '15},
-}
-
-@article{takach16_high_level_synth,
- author = {A. {Takach}},
- title = {High-Level Synthesis: Status, Trends, and Future
- Directions},
- journal = {IEEE Design Test},
- volume = {33},
- number = {3},
- pages = {116-124},
- year = {2016},
- doi = {10.1109/MDAT.2016.2544850},
- ISSN = {2168-2364},
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-}
-
-@inproceedings{liu16_effic_high_level_synth_desig,
- author = { {Dong Liu} and B. C. {Schafer}},
- title = {Efficient and reliable High-Level Synthesis Design Space
- Explorer for FPGAs},
- booktitle = {2016 26th International Conference on Field Programmable
- Logic and Applications (FPL)},
- year = 2016,
- pages = {1-8},
- doi = {10.1109/FPL.2016.7577370},
- ISSN = {1946-1488},
- month = {Aug},
-}
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-@article{lahti19_are_we_there_yet,
- author = {S. {Lahti} and P. {Sj{\"o}vall} and J. {Vanne} and
- T. D. {H{\"a}m{\"a}l{\"a}inen}},
- title = {Are We There Yet? a Study on the State of High-Level
- Synthesis},
- journal = {IEEE Transactions on Computer-Aided Design of Integrated
- Circuits and Systems},
- volume = {38},
- number = {5},
- pages = {898-911},
- year = {2019},
- doi = {10.1109/TCAD.2018.2834439},
- ISSN = {1937-4151},
- month = {May},
-}
-
-@misc{mentor20_catap_high_level_synth,
- author = {Mentor},
- title = {Catapult High-Level Synthesis},
- url = {https://bit.ly/32xhADw},
- urldate = {2020-06-06},
- year = 2020,
-}
-
-@misc{xilinx20_vivad_high_synth,
- author = {Xilinx},
- title = {Vivado High-level Synthesis},
- url = {https://bit.ly/39ereMx},
- urldate = {2020-07-20},
- year = 2020,
-}
-
-@misc{intel20_sdk_openc_applic,
- author = {Intel},
- title = {{SDK} for {OpenCL} Applications},
- url = {https://intel.ly/30sYHz0},
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- year = 2020,
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-@inproceedings{gupta03_spark,
- author = {S. {Gupta} and N. {Dutt} and R. {Gupta} and A. {Nicolau}},
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- transformations},
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- year = 2003,
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- author = {R. {Chouksey} and C. {Karfa}},
- title = {Verification of Scheduling of Conditional Behaviors in
- High-Level Synthesis},
- journal = {IEEE Transactions on Very Large Scale Integration (VLSI)
- Systems},
- volume = {},
- number = {},
- pages = {1-14},
- year = {2020},
- doi = {10.1109/TVLSI.2020.2978242},
- ISSN = {1557-9999},
- month = {},
-}
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-@inproceedings{pnueli98_trans,
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-@article{chouksey19_trans_valid_code_motion_trans_invol_loops,
- author = {R. {Chouksey} and C. {Karfa} and P. {Bhaduri}},
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- Involving Loops},
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- Circuits and Systems},
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- author = { Kim, Y. and {Kopuri}, S. and {Mansouri}, N.},
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- finite state machines with datapath (FSMD)},
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- year = 2004,
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- author = {Karfa, C. and Mandal, C. and Sarkar, D. and Pentakota, S. R. and
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- year = 2006,
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- acmid = 1126731,
- address = {Washington, DC, USA},
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- series = {ISQED '06},
-}
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- author = {Leroy, Xavier},
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- on Principles of Programming Languages},
- year = 2006,
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-@inproceedings{loow19_verif_compil_verif_proces,
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- Myreen, Magnus O. and Norrish, Michael and Abrahamsson, Oskar
- and Fox, Anthony},
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- Language Design and Implementation},
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-@article{canis13_legup,
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- Kammoona, Ahmed and Czajkowski, Tomasz and Brown, Stephen D. and Anderson, Jason
- H.},
- title = {Legup: an Open-Source High-Level Synthesis Tool for Fpga-Based
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- keywords = {High-level synthesis, FPGAs, hardware/software codesign, synthesis,
- performance, power, field-programmable gate arrays},
- month = sep,
- numpages = {27},
- publisher = {Association for Computing Machinery},
-}
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- pages = {8-17},
- year = 2009,
- doi = {10.1109/MDT.2009.69},
- keywords = {high level synthesis;high-level synthesis;optimized RTL
- hardware;abstraction level design;HLS techniques;High level
- synthesis;Assembly;Application software;Circuit
- simulation;Design methodology;Space exploration;Computer
- architecture;Design optimization;Hardware design
- languages;Circuit synthesis;high-level synthesis;RTL
- abstraction;custom processors;hardware synthesis and
- verification;architectures;design and test},
- month = {July},
-}
-
-@article{aubury96_handel_c_languag_refer_guide,
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- Jonathan and Watts, Robin},
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- year = 1996,
-}
-
-@inproceedings{clarke03_behav_c_veril,
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- month = {June},
-}
-
-@inproceedings{josipovic18_dynam_sched_high_level_synth,
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- Gate Arrays},
- year = 2018,
- pages = {127-136},
- doi = {10.1145/3174243.3174264},
- address = {New York, NY, USA},
- isbn = 9781450356145,
- keywords = {dynamically scheduled circuits, compiler, pipelining, high-level synthesis},
- location = {Monterey, CALIFORNIA, USA},
- numpages = 10,
- publisher = {Association for Computing Machinery},
- series = {FPGA '18},
-}
-
-@inproceedings{cheng20_combin_dynam_static_sched_high_level_synth,
- author = {Cheng, Jianyi and Josipovic, Lana and Constantinides, George A. and Ienne,
- Paolo and Wickerson, John},
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- year = 2020,
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- doi = {10.1145/3373087.3375297},
- address = {New York, NY, USA},
- isbn = 9781450370998,
- keywords = {high-level synthesis, dynamic scheduling, static analysis},
- location = {Seaside, CA, USA},
- numpages = 11,
- publisher = {Association for Computing Machinery},
- series = {FPGA '20},
-}
-
-@article{josipovic17_out_of_order_load_store,
- author = {Josipovic, Lana and Brisk, Philip and Ienne, Paolo},
- title = {An Out-Of-Order Load-Store Queue for Spatial Computing},
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- volume = {16},
- number = {5s},
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- address = {New York, NY, USA},
- articleno = {125},
- issn = {1539-9087},
- issue_date = {October 2017},
- keywords = {Load-store queue, dynamic scheduling, allocation, spatial computing},
- month = sep,
- numpages = {19},
- publisher = {Association for Computing Machinery},
-}
-
-@inproceedings{josipovic20_buffer_placem_sizin_high_perfor_dataf_circuit,
- author = {Josipovi\'{c}, Lana and Sheikhha, Shabnam and Guerrieri, Andrea and Ienne,
- Paolo and Cortadella, Jordi},
- title = {Buffer Placement and Sizing for High-Performance Dataflow Circuits},
- booktitle = {The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
- year = 2020,
- pages = {186-196},
- doi = {10.1145/3373087.3375314},
- address = {New York, NY, USA},
- isbn = 9781450370998,
- keywords = {buffers, high-level synthesis, dataflow circuits, timing optimization},
- location = {Seaside, CA, USA},
- numpages = 11,
- publisher = {Association for Computing Machinery},
- series = {FPGA '20},
-}
-
-@article{leroy09_formal_verif_compil_back_end,
- author = {Leroy, Xavier},
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- and Implementation},
- year = 2011,
- pages = {283-294},
- doi = {10.1145/1993498.1993532},
- address = {New York, NY, USA},
- isbn = 9781450306638,
- keywords = {random program generation, compiler defect, automated testing, compiler
- testing, random testing},
- location = {San Jose, California, USA},
- numpages = 12,
- publisher = {Association for Computing Machinery},
- series = {PLDI '11},
-}
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- title = {Interactive Theorem Proving and Program Development},
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- publisher = {Springer Berlin Heidelberg},
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-}
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-}
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- year = 2020,
- doi = {10.1145/3373087.3375310},
- isbn = {978-1-4503-7099-8/20/02},
- keywords = {automated testing, compiler defect, compiler testing, random program
- generation, random testing},
- location = {Seaside, CA, USA},
- numpages = 11,
-}
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- title = {{Vivado Design Suite}},
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-}
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- author = {Intel},
- title = {{Intel Quartus}},
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- {https://intel.ly/2m7wbCs},
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- year = 2019,
-}
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- author = {Clifford Wolf},
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- author = {Tristan, Jean-Baptiste and Leroy, Xavier},
- title = {Formal Verification of Translation Validators: A Case Study on
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- Principles of Programming Languages},
- year = 2008,
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- compilers, scheduling optimizations},
- location = {San Francisco, California, USA},
- numpages = 11,
- publisher = {Association for Computing Machinery},
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- Programming Languages},
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- series = {POPL '73},
-}
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- Based on Dataflow Analysis",
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- year = 2006,
- pages = "66--81",
- address = "Berlin, Heidelberg",
- editor = "Filli{\^a}tre, Jean-Christophe and Paulin-Mohring,
- Christine and Werner, Benjamin",
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- publisher = "Springer",
-}
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- author = {R. {Chouksey} and C. {Karfa} and P. {Bhaduri}},
- title = {Translation Validation of Code Motion Transformations
- Involving Loops},
- tags = {hls, verification},
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- Circuits and Systems},
- volume = 38,
- number = 7,
- pages = {1378-1382},
- year = 2019,
- doi = {10.1109/TCAD.2018.2846654},
- ISSN = {1937-4151},
- month = {July},
-}
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-@inproceedings{karfa07_hand_verif_high_synth,
- author = {Karfa, C. and Sarkar, D. and Mandal, C.
- and Reade, C.},
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- year = 2007,
- pages = {429--434},
- doi = {10.1145/1228784.1228885},
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- address = {New York, NY, USA},
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- location = {Stresa-Lago Maggiore, Italy},
- numpages = 6,
- publisher = {ACM},
- series = {GLSVLSI '07},
-}
-
-@article{karfa08_equiv_check_method_sched_verif,
- author = {C. {Karfa} and D. {Sarkar} and C. {Mandal} and P. {Kumar}},
- title = {An Equivalence-Checking Method for Scheduling Verification in
- High-Level Synthesis},
- tags = {hls, verification},
- journal = {IEEE Transactions on Computer-Aided Design of Integrated
- Circuits and Systems},
- volume = 27,
- number = 3,
- pages = {556-569},
- year = 2008,
- doi = {10.1109/TCAD.2007.913390},
- ISSN = {1937-4151},
- month = {March},
-}
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-@article{karfa10_verif_datap_contr_gener_phase,
- author = {C. {Karfa} and D. {Sarkar} and C. {Mandal}},
- title = {Verification of Datapath and Controller Generation Phase in
- High-Level Synthesis of Digital Circuits},
- tags = {hls, verification},
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- Circuits and Systems},
- volume = 29,
- number = 3,
- pages = {479-492},
- year = 2010,
- doi = {10.1109/TCAD.2009.2035542},
- ISSN = {1937-4151},
- month = {March},
-}
-
-@article{karfa12_formal_verif_code_motion_techn,
- author = {Karfa, C. and Mandal, C. and Sarkar, D.},
- title = {Formal Verification of Code Motion Techniques Using
- Data-Flow-Driven Equivalence Checking},
- tags = {hls, verification},
- journal = {ACM Trans. Des. Autom. Electron. Syst.},
- volume = 17,
- number = 3,
- year = 2012,
- doi = {10.1145/2209291.2209303},
- address = {New York, NY, USA},
- articleno = {Article 30},
- issn = {1084-4309},
- issue_date = {June 2012},
- month = jul,
- numpages = 37,
- publisher = {Association for Computing Machinery},
-}
-
-@article{chouksey20_verif_sched_condit_behav_high_level_synth,
- author = {R. {Chouksey} and C. {Karfa}},
- title = {Verification of Scheduling of Conditional Behaviors in
- High-Level Synthesis},
- journal = {IEEE Transactions on Very Large Scale Integration (VLSI)
- Systems},
- volume = {},
- number = {},
- pages = {1-14},
- year = {2020},
- doi = {10.1109/TVLSI.2020.2978242},
- ISSN = {1557-9999},
- month = {},
-}
-
-@inproceedings{kundu08_valid_high_level_synth,
- author = "Kundu, Sudipta and Lerner, Sorin and Gupta, Rajesh",
- title = "Validating High-Level Synthesis",
- booktitle = "Computer Aided Verification",
- year = 2008,
- pages = "459--472",
- address = "Berlin, Heidelberg",
- editor = "Gupta, Aarti and Malik, Sharad",
- isbn = "978-3-540-70545-1",
- publisher = "Springer Berlin Heidelberg",
-}
-
-@inproceedings{kundu07_autom,
- author = { {Sudipta Kundu} and S. {Lerner} and {Rajesh Gupta}},
- title = {Automated refinement checking of concurrent systems},
- booktitle = {2007 IEEE/ACM International Conference on Computer-Aided Design},
- year = 2007,
- pages = {318-325},
- doi = {10.1109/ICCAD.2007.4397284},
- ISSN = {1558-2434},
- month = {Nov},
-}
-
-@inproceedings{tristan10_simpl_verif_valid_softw_pipel,
- author = {Tristan, Jean-Baptiste and Leroy, Xavier},
- location = {Madrid, Spain},
- publisher = {Association for Computing Machinery},
- url = {https://doi.org/10.1145/1706299.1706311},
- booktitle = {Proceedings of the 37th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages},
- year = {2010},
- doi = {10.1145/1706299.1706311},
- isbn = {9781605584799},
- keywords = {symbolic execution,coq,verification,translation validation,loop scheduling,compiler optimisation,software pipelining},
- pages = {83--92},
- series = {POPL '10},
- title = {A Simple, Verified Validator for Software Pipelining}
-}
-
-@article{barthe14_formal_verif_ssa_based_middl_end_compc,
- abstract = {CompCert is a formally verified compiler that generates compact and efficient code for a large subset of the C language. However, CompCert foregoes using SSA, an intermediate representation employed by many compilers that enables writing simpler, faster optimizers. In fact, it has remained an open problem to verify formally an SSA-based compiler. We report on a formally verified, SSA-based middle-end for CompCert. In addition to providing a formally verified SSA-based middle-end, we address two problems raised by Leroy in [2009]: giving an intuitive formal semantics to SSA, and leveraging its global properties to reason locally about program optimizations.},
- author = {Barthe, Gilles and Demange, Delphine and Pichardie, David},
- location = {New York, NY, USA},
- publisher = {Association for Computing Machinery},
- url = {https://doi.org/10.1145/2579080},
- date = {2014-03},
- doi = {10.1145/2579080},
- issn = {0164-0925},
- journaltitle = {ACM Trans. Program. Lang. Syst.},
- keywords = {CompCertSSA,CompCert,SSA,coq,verification,compiler optimisation},
- number = {1},
- title = {Formal Verification of an SSA-Based Middle-End for CompCert},
- volume = {36}
-}
-
-@inproceedings{ottenstein90_progr_depen_web,
- abstract = {The Program Dependence Web (PDW) is a program representation that can be directly interpreted using control-, data-, or demand-driven models of execution. A PDW combines a single-assignment version of the program with explicit operators that manage the flow of data values. The PDW can be viewed as an augmented Program Dependence Graph. Translation to the PDW representation provides the basis for projects to compile Fortran onto dynamic dataflow architectures and simulators. A second application of the PDW is the construction of various compositional semantics for program dependence graphs.},
- author = {Ottenstein, Karl J. and Ballance, Robert A. and MacCabe, Arthur B.},
- location = {White Plains, New York, USA},
- publisher = {Association for Computing Machinery},
- url = {https://doi.org/10.1145/93542.93578},
- booktitle = {Proceedings of the ACM SIGPLAN 1990 Conference on Programming Language Design and Implementation},
- date = {1990},
- doi = {10.1145/93542.93578},
- isbn = {0897913647},
- keywords = {gated-SSA,SSA,program dependence graph},
- pages = {257--271},
- series = {PLDI '90},
- title = {The Program Dependence Web: A Representation Supporting Control-, Data-, and Demand-Driven Interpretation of Imperative Languages}
-}
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