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@@ -1410,3 +1410,34 @@
 	year = {2013}
 }
 
+@inproceedings{zhang13_sdc,
+	abstract = {Modulo scheduling is a popular technique to enable pipelined execution of successive loop iterations for performance improvement. While a variety of modulo scheduling algorithms exist for software pipelining, they are not amenable to many complex design constraints and optimization goals that arise in the hardware synthesis context. In this paper we describe a modulo scheduling framework based on the formulation of system of difference constraints (SDC). Our framework can systematically model a rich set of performance constraints that are specific to the hardware design. The scheduler also exploits the unique mathematical properties of SDC to carry out efficient global optimization and fast incremental update on the constraint system to minimize the resource usage of the synthesized pipeline. Experiments demonstrate that our proposed technique provides efficient solutions for a set of real-life applications and compares favorably against a widely used lifetime-sensitive modulo scheduling algorithm.},
+	author = {Zhang, Z. and Liu, B.},
+	url = {https://doi.org/10.1109/ICCAD.2013.6691121},
+	booktitle = {2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
+	doi = {10.1109/ICCAD.2013.6691121},
+	issn = {1558-2434},
+	keywords = {high level synthesis;pipeline processing;scheduling;SDC-based modulo scheduling;pipeline synthesis;hardware design;mathematical properties;global optimization;incremental update;Schedules;Pipeline processing;Registers;Optimal scheduling;Scheduling algorithms;Timing},
+	month = nov,
+	pages = {211--218},
+	title = {SDC-based modulo scheduling for pipeline synthesis},
+	year = {2013}
+}
+
+@inproceedings{ball93_branc_predic_free,
+	keywords = {if-conversion},
+	author = {Ball, Thomas and Larus, James R.},
+	title = {Branch Prediction for Free},
+	year = {1993},
+	isbn = {0897915984},
+	publisher = {Association for Computing Machinery},
+	address = {New York, NY, USA},
+	url = {https://doi.org/10.1145/155090.155119},
+	doi = {10.1145/155090.155119},
+	abstract = {Many compilers rely on branch prediction to improve program performance by identifying frequently executed regions and by aiding in scheduling instructions.Profile-based predictors require a time-consuming and inconvenient compile-profile-compile cycle in order to make predictions. We present a program-based branch predictor that performs well for a large and diverse set of programs written in C and Fortran. In addition to using natural loop analysis to predict branches that control the iteration of loops, we focus on heuristics for predicting non-loop branches, which dominate the dynamic branch count of many programs. The heuristics are simple and require little program analysis, yet they are effective in terms of coverage and miss rate. Although program-based prediction does not equal the accuracy of profile-based prediction, we believe it reaches a sufficiently high level to be useful. Additional type and semantic information available to a compiler would enhance our heuristics.},
+	booktitle = {Proceedings of the ACM SIGPLAN 1993 Conference on Programming Language Design and Implementation},
+	pages = {300–313},
+	numpages = {14},
+	location = {Albuquerque, New Mexico, USA},
+	series = {PLDI '93}
+}