Add pipelining text

1 files changed, 76 insertions, 0 deletions

diff --git a/lsr_refs.bib b/lsr_refs.bib
index f9cf0d3..abfd180 100644
--- a/lsr_refs.bib
+++ b/lsr_refs.bib
@@ -723,6 +723,23 @@
 	year = {2019}
 }
 
+@inproceedings{lam88_softw_pipel,
+	author = {Lam, M.},
+	title = {Software Pipelining: An Effective Scheduling Technique for VLIW Machines},
+	year = {1988},
+	isbn = {0897912691},
+	publisher = {Association for Computing Machinery},
+	address = {New York, NY, USA},
+	url = {https://doi.org/10.1145/53990.54022},
+	doi = {10.1145/53990.54022},
+	abstract = {This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipelining is that optimal performance can be achieved with compact object code.This paper extends previous results of software pipelining in two ways: First, this paper shows that by using an improved algorithm, near-optimal performance can be obtained without specialized hardware. Second, we propose a hierarchical reduction scheme whereby entire control constructs are reduced to an object similar to an operation in a basic block. With this scheme, all innermost loops, including those containing conditional statements, can be software pipelined. It also diminishes the start-up cost of loops with small number of iterations. Hierarchical reduction complements the software pipelining technique, permitting a consistent performance improvement be obtained.The techniques proposed have been validated by an implementation of a compiler for Warp, a systolic array consisting of 10 VLIW processors. This compiler has been used for developing a large number of applications in the areas of image, signal and scientific processing.},
+	booktitle = {Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation},
+	pages = {318–328},
+	numpages = {11},
+	location = {Atlanta, Georgia, USA},
+	series = {PLDI '88}
+}
+
 @inproceedings{leroy06_formal_certif_compil_back_end,
 	author = {Leroy, Xavier},
 	location = {Charleston, South Carolina, USA},
@@ -1067,6 +1084,65 @@
 	year = {2013}
 }
 
+@inproceedings{rau92_code_gener_schem_sched_loops,
+	author = {Rau, B. Ramakrishna and Schlansker, Michael S. and Tirumalai, P. P.},
+	location = {Portland, Oregon, USA},
+	publisher = {IEEE Computer Society Press},
+	booktitle = {Proceedings of the 25th Annual International Symposium on Microarchitecture},
+	isbn = {0818631759},
+	keywords = {modulo scheduling,code motion,loop scheduling,software pipelining,rotating registers},
+	pages = {158--169},
+	series = {MICRO 25},
+	title = {Code Generation Schema for modulo Scheduled Loops},
+	year = {1992}
+}
+
+@inproceedings{rau92_regis_alloc_softw_pipel_loops,
+	abstract = {Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. This paper studies the task of register allocation for software pipelined loops, both with and without hardware features that are specifically aimed at supporting software pipelines. Register allocation for software pipelines presents certain novel problems leading to unconventional solutions, especially in the presence of hardware support. This paper formulates these novel problems and presents a number of alternative solution strategies. These alternatives are comprehensively tested against over one thousand loops to determine the best register allocation strategy, both with and without the hardware support for software pipelining.},
+	author = {Rau, B. R. and Lee, M. and Tirumalai, P. P. and Schlansker, M. S.},
+	location = {San Francisco, California, USA},
+	publisher = {Association for Computing Machinery},
+	url = {https://doi.org/10.1145/143095.143141},
+	booktitle = {Proceedings of the ACM SIGPLAN 1992 Conference on Programming Language Design and Implementation},
+	doi = {10.1145/143095.143141},
+	isbn = {0897914759},
+	keywords = {software pipelining,loop scheduling,register allocation,rotating registers,compiler optimisation},
+	pages = {283--299},
+	series = {PLDI '92},
+	title = {Register Allocation for Software Pipelined Loops},
+	year = {1992}
+}
+
+@inproceedings{rau94_iterat_sched,
+	abstract = {Modulo scheduling is a framework within which a wide variety of algorithms and heuristics may be defined for software pipelining innermost loops. This paper presents a practical algorithm, iterative modulo scheduling, that is capable of dealing with realistic machine models. This paper also characterizes the algorithm in terms of the quality of the generated schedules as well the computational expense incurred.},
+	author = {Rau, B. Ramakrishna},
+	location = {San Jose, California, USA},
+	publisher = {Association for Computing Machinery},
+	url = {https://doi.org/10.1145/192724.192731},
+	booktitle = {Proceedings of the 27th Annual International Symposium on Microarchitecture},
+	doi = {10.1145/192724.192731},
+	isbn = {0897917073},
+	keywords = {software pipelining,loop scheduling,rotating registers,code motion,compiler optimisation,modulo scheduling},
+	pages = {63--74},
+	series = {MICRO 27},
+	title = {Iterative modulo Scheduling: An Algorithm for Software Pipelining Loops},
+	year = {1994}
+}
+
+@article{rau96_iterat_modul_sched,
+	abstract = {Modulo scheduling is a framework within which algorithms for software pipelining innermost loops may be defined. The framework specifies a set of constraints that must be met in order to achieve a legal modulo schedule. A wide variety of algorithms and heuristics can be defined within this framework. Little work has been done to evaluate and compare alternative algorithms and heuristics for modulo scheduling from the viewpoints of schedule quality as well as computational complexity. This, along with a vague and unfounded perception that modulo scheduling is computationally expensive as well as difficult to implement, have inhibited its incorporation into product compilers. This paper presents iterative modulo scheduling, a practical algorithm that is capable of dealing with realistic machine models. The paper also characterizes the algorithm in terms of the quality of the generated schedules as well the computational expense incurred.},
+	author = {Rau, B. Ramakrishna},
+	url = {https://doi.org/10.1007/BF03356742},
+	date = {1996-02-01},
+	issn = {1573-7640},
+	journaltitle = {International Journal of Parallel Programming},
+	keywords = {loop scheduling,software pipelining,code motion,compiler optimisation,rotating registers,modulo scheduling},
+	number = {1},
+	pages = {3--64},
+	title = {Iterative Modulo Scheduling},
+	volume = {24}
+}
+
 @inproceedings{schuiki20_llhd,
 	author = {Schuiki, Fabian and Kurth, Andreas and Grosser, Tobias and Benini, Luca},
 	location = {London, UK},