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\chapter{Conclusion}
+Vericert is currently a fully verified but simple \HLS\ tool. For the rest of my PhD, the goal will
+be to improve the throughput of the designs that are generated by Vericert, by first parallelising
+instructions using scheduling on hyperblocks, as well as introducing modulo scheduling to handle
+loops. One other possible extension could be to collaborate with Sandrine Blazy and Delphine
+Demange to implement a dynamic \HLS\ tool using \GSA\ as a base representation.
+
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