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Diffstat (limited to 'chapters/hls.tex')
| -rw-r--r-- | chapters/hls.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chapters/hls.tex b/chapters/hls.tex index 7e1f79e..0be3f99 100644 --- a/chapters/hls.tex +++ b/chapters/hls.tex @@ -187,7 +187,7 @@ always-blocks triggering on the same event are executed in parallel. Always-bloc control-flow using if-statements and case-statements. \startplacemarginfigure[reference={fig:tutorial:state_machine},title={Example of a state machine - implementation in Verilog and it's corresponding state diagram.}] + implementation in Verilog and its corresponding state diagram.}] \startfloatcombination[nx=2, ny=1] \startplacesubfigure \startframedtext[width={0.6\textwidth},frame=off,offset=none,bodyfont=11pt] @@ -242,7 +242,7 @@ simultaneously. The first always-block controls the values in the register \typ When the \type{state} is 0, \type{tmp} will be assigned to the input \type{y} using nonblocking assignment, denoted by \type{<=}. Nonblocking assignment assigns registers in parallel at the end of the clock cycle, rather than sequentially throughout the always-block. In the second -always-block, the input \type{y} will be checked, and if it's high it will move on to the next +always-block, the input \type{y} will be checked, and if it is high it will move on to the next state, otherwise it will stay in the current state. When \type{state} is 1, the first always-block will reset the value of \type{tmp} and then set \type{z} to the original value of \type{tmp}, since nonblocking assignment does not change its value until the end of the clock cycle. Finally, the |