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index 1ed2e1f..03e91cc 100644
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+++ b/references.bib
@@ -683,8 +683,7 @@ year = {2020},
}
@inproceedings{meredith10_veril,
- author = {P. {Meredith} and M. {Katelman} and J. {Meseguer} and
- G. {Ro{\c{s}}u}},
+ author = {{Meredith}, P. and {Katelman}, M. and {Meseguer}, J. and {Ro{\c{s}}u} G.},
title = {A formal executable semantics of {Verilog}},
tags = {semantics},
booktitle = {Eighth ACM/IEEE International Conference on Formal Methods and
@@ -761,7 +760,7 @@ year = {2020},
}
@inproceedings{nikhil04_blues_system_veril,
- author = {R. {Nikhil}},
+ author = {{Nikhil}, R.},
title = {Bluespec System Verilog: efficient, correct RTL from high level specifications},
booktitle = {Proceedings. Second ACM and IEEE International Conference on Formal Methods and
Models for Co-Design, 2004. MEMOCODE '04.},
@@ -968,7 +967,7 @@ series = {CPP 2021}
@inproceedings{noronha17_rapid_fpga,
keywords = {high-level synthesis, FPGA, inlining, compiler optimisation},
- author = {D. H. {Noronha} and J. P. {Pinilla} and S. J. E. {Wilton}},
+ author = {{Noronha}, D. H. and {Pinilla}, J. P. and {Wilton}, S. J. E.},
booktitle = {2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
title = {Rapid circuit-specific inlining tuning for FPGA high-level synthesis},
year = {2017},