Remove link macro

2 files changed, 9 insertions, 15 deletions

diff --git a/documentation.org b/documentation.org
index 5740318..2812d9f 100644
--- a/documentation.org
+++ b/documentation.org
@@ -26,16 +26,16 @@ have all been proven correct, providing a verified translation from C to Verilog
 
 ** Content
 
-- {{{link([[/docs/building/][Vericert Documentation]],[[#building][Vericert Documentation]])}}}
+- [[#building][Vericert Documentation]]
 
 ** Papers
 
 - OOPSLA '21 :: Yann Herklotz, James D. Pollard, Nadesh Ramanathan, and John Wickerson. Formal
-  Verification of High-Level Synthesis. In /Proc. ACM Program. Lang./ 5, OOPSLA, 2021. [{{{link([[/papers/fvhls_oopsla21.pdf][pdf]],[[./static/papers/fvhls_oopsla21.pdf][pdf]])}}}]
+  Verification of High-Level Synthesis. In /Proc. ACM Program. Lang./ 5, OOPSLA, 2021. [[[./static/papers/fvhls_oopsla21.pdf][pdf]]]
 
 - LATTE '21 :: Yann Herklotz and John Wickerson. High-level synthesis tools should be proven
   correct. In /Workshop on Languages, Tools, and Techniques for Accelerator
-  Design/, 2021. [{{{link([[/papers/hlsspc_latte2021.pdf][pdf]],[[./static/papers/hlsspc_latte2021.pdf][pdf]])}}}]
+  Design/, 2021. [[[./static/papers/hlsspc_latte2021.pdf][pdf]]]
 
 ** Mailing lists
 
@@ -50,8 +50,8 @@ For contributing patches to the [[https://sr.ht/~ymherklotz/vericert/][sourcehut
 :EXPORT_HUGO_CUSTOM_FRONT_MATTER: :headless true
 :END:
 
-- {{{link([[/docs/][Docs]],[[#docs][Docs]])}}}
-  - {{{link([[/docs/building/][Building]],[[#building][Building]])}}}
+- [[#docs][Docs]]
+  - [[#building][Building]]
 
 * Documentation
 
@@ -69,7 +69,7 @@ application-specific integrated circuit (ASIC).
 #+attr_html: :width 600
 #+caption: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.
 #+name: fig:design
-{{{link([[/images/toolflow.svg]],[[./static/images/toolflow.svg]])}}}
+[[./static/images/toolflow.svg]]
 
 The design shown in Figure [[fig:design]] shows how Vericert leverages an existing verified C compiler
 called [[https://compcert.org/compcert-C.html][CompCert]] to perform this translation.
@@ -634,7 +634,7 @@ A small standalone Coq file that exhibits many of the style points.
 
 Blog posts:
 
-** A First Look at Vericert :introduction:summary:@article:
+** A First Look at Vericert :introduction:summary:article:
 :PROPERTIES:
 :EXPORT_DATE: 2021-10-09
 :EXPORT_FILE_NAME: a-first-look-at-vericert
@@ -751,7 +751,7 @@ to reason about the RAM when it isn't enabled.
 
 *** Useful links
 
-- {{{link([[/papers/fvhls_oopsla21.pdf][OOPSLA'21 preprint]],[[./static/papers/fvhls_oopsla21.pdf][OOPSLA'21 preprint]])}}}.
+- [[./static/papers/fvhls_oopsla21.pdf][OOPSLA'21 preprint]].
 - [[https://youtu.be/clPiKbKVlUA][OOPSLA'21 presentation]].
 - [[https://github.com/ymherklotz/vericert][Github repository]].
 
diff --git a/publish.el b/publish.el
index fab3ec0..e50fccc 100644
--- a/publish.el
+++ b/publish.el
@@ -9,13 +9,7 @@
 (require 'ox)
 (require 'ox-hugo)
 
-(setq org-export-use-babel 'inline-only
-      org-confirm-babel-evaluate nil
+(setq org-confirm-babel-evaluate nil
       org-export-with-broken-links t)
 
-(defun ymhg/link (arg1 arg2)
-  (cond
-   ((eq 'hugo org-export-current-backend) arg1)
-   (t arg2)))
-
 (org-hugo-export-wim-to-md :all-subtrees)