Fix printing of the final cycle count

1 files changed, 15 insertions, 2 deletions

diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index e67b567..aeaf75c 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -181,6 +181,7 @@ let testbench = "module testbench;
    reg start, reset, clk;
    wire finish;
    wire [31:0] return_val;
+   reg [31:0] cycles;
 
    main m(start, reset, clk, finish, return_val);
 
@@ -190,20 +191,23 @@ let testbench = "module testbench;
       reset = 0;
       @(posedge clk) reset = 1;
       @(posedge clk) reset = 0;
+      cycles = 0;
    end
 
    always #5 clk = ~clk;
 
    always @(posedge clk) begin
       if (finish == 1) begin
+         $display(\"cycles: %0d\", cycles);
          $display(\"finished: %0d\", return_val);
          $finish;
       end
+      cycles <= cycles + 1;
    end
 endmodule
 "
 
-let debug_always i clk state = concat [
+let debug_always_verbose i clk state = concat [
     indent i; "reg [31:0] count;\n";
     indent i; "initial count = 0;\n";
     indent i; "always @(posedge " ^ register clk ^ ") begin\n";
@@ -215,6 +219,15 @@ let debug_always i clk state = concat [
     indent i; "end\n"
   ]
 
+let debug_always i clk finish = concat [
+    indent i; "reg [31:0] count;\n";
+    indent i; "initial count = 0;\n";
+    indent i; "always @(posedge " ^ register clk ^ ") begin\n";
+    indent (i+2); "if(" ^ register finish ^ ") $display(\"Cycles: %0d\", count);\n";
+    indent (i+1); "count <= count + 1;\n";
+    indent i; "end\n"
+  ]
+
 let print_initial i n stk = concat [
     indent i; "integer i;\n";
     indent i; "initial for(i = 0; i < "; sprintf "%d" n; "; i++)\n";
@@ -234,7 +247,7 @@ let pprint_module debug i n m =
              "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n";
              fold_map (pprint_module_item (i+1)) m.mod_body;
              if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else "";
-             if debug then debug_always i m.mod_clk m.mod_st else "";
+             if debug then debug_always_verbose i m.mod_clk m.mod_st else "";
              indent i; "endmodule\n\n"
            ]
   else ""