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* Get some Verilog output with dividersdev/dividerYann Herklotz2021-02-222-11/+22
* Fix Scheduling to add missing statesYann Herklotz2021-02-221-14/+34
* Fix arguments to RBassign and pipedYann Herklotz2021-02-224-5/+10
* Add operation pipeliningYann Herklotz2021-02-222-8/+137
* Add RTLPar printingYann Herklotz2021-02-225-4/+84
* Add operator pipelining passYann Herklotz2021-02-211-0/+67
* Add new instructions for pipelinesYann Herklotz2021-02-219-24/+33
* Correctly add initial scheduling variablesYann Herklotz2021-02-211-4/+20
* Merge branch 'develop' into dev/dividerYann Herklotz2021-02-2116-276/+1187
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| * Fix printing of the final cycle countYann Herklotz2021-02-211-2/+15
| * Fix bug in scheduleYann Herklotz2021-02-191-2/+1
| * Fix schedule for nowYann Herklotz2021-02-181-1/+2
| * Add udiv and sdiv to constraintsYann Herklotz2021-02-171-12/+20
| * Remove dead code and add more constraintsYann Herklotz2021-02-171-107/+16
| * Add option to turn off if-conversionYann Herklotz2021-02-167-6/+33
| * Merge branch 'master' into developYann Herklotz2021-02-165-12/+623
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| | * Remove the documentation stagesYann Herklotz2021-02-161-8/+0
| | * Pin nixpkgsYann Herklotz2021-02-161-2/+1
| | * Use dune_2 insteadYann Herklotz2021-02-161-1/+1
| | * Remove dependency on TacticsYann Herklotz2021-02-161-1/+0
| | * Add functional units and SatYann Herklotz2021-02-162-0/+621
| * | Use topological sort for nowYann Herklotz2021-02-161-4/+9
| * | Add schedule for new RTLPar typeYann Herklotz2021-02-161-29/+42
| * | Fix RTLPar to use instr list list listYann Herklotz2021-02-163-25/+33
| * | Replace original gather function with new constraintsYann Herklotz2021-02-151-15/+16
| * | Add resource constraintsYann Herklotz2021-02-151-6/+71
| * | Add information about pipeline and comb_delayYann Herklotz2021-02-151-8/+41
| * | Add data and control dependencies to reworked graphYann Herklotz2021-02-151-43/+236
| * | Make the schedule a bit neaterYann Herklotz2021-02-151-74/+63
| * | Use proper graph for DFGYann Herklotz2021-02-151-77/+113
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* / Add beginning to scheduling divisionYann Herklotz2021-02-157-310/+181
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* Add more legible names to variablesmichalis_merge_2dev/improved-namesYann Herklotz2021-02-121-1/+17
* Add signed and unsigned divisionYann Herklotz2021-02-122-0/+339
* Add temporary fixes to get everything to compiledev/predicated-executionYann Herklotz2021-02-129-45/+514
* Fix state generation for if-conversionYann Herklotz2021-02-034-14/+21
* Fix scheduling for if-conversionYann Herklotz2021-02-031-14/+90
* Add predicated values and instructionsYann Herklotz2021-02-027-41/+92
* Add if conversion passYann Herklotz2021-02-021-3/+65
* Add if conversion passYann Herklotz2021-02-021-0/+32
* Add Vrange and predicatesYann Herklotz2021-02-028-66/+95
* Fix OCaml files for compilationYann Herklotz2021-01-314-92/+94
* Fix compilation of CoqYann Herklotz2021-01-302-19/+48
* Fix proofs with better defined equalityYann Herklotz2021-01-302-31/+57
* Fix definitions of proofs some moreYann Herklotz2021-01-294-106/+162
* Fix the proof for RTLPargenYann Herklotz2021-01-291-32/+33
* Fix HTLPargen and RTLPargenYann Herklotz2021-01-292-56/+178
* Refactoring RTLBlock and RTLParYann Herklotz2021-01-293-297/+205
* Finish all proofs except executing basic blocksYann Herklotz2021-01-271-1/+4
* Add more proofs for RTLPargen correctnessYann Herklotz2021-01-273-26/+97
* Add basic block matching and proofYann Herklotz2021-01-261-3/+78
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