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| author | Yann Herklotz <git@yannherklotz.com> | 2021-07-24 16:09:09 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-24 16:10:15 +0200 |
| commit | 0c021173b3efb1310370de4b2a6f5444c745022f (patch) | |
| tree | c1aeebc65a68d05f9de629f27f7e426035c263f7 | |
| parent | 3496f507d97547c8f544be8219768b000cadb840 (diff) | |
| download | vericert-kvx-oopsla21.tar.gz vericert-kvx-oopsla21.zip | |
Use main instead of top for synthesising Vericert designsoopsla21
| -rw-r--r-- | scripts/synth.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/scripts/synth.tcl b/scripts/synth.tcl index 2b032be..e5151e8 100644 --- a/scripts/synth.tcl +++ b/scripts/synth.tcl @@ -77,7 +77,7 @@ proc dump_statistics { } { set outputDir . create_project -in_memory -part xc7z020clg484-1 -force read_verilog main.v -synth_design -mode out_of_context -no_iobuf -top top -part xc7z020clg484-1 +synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1 write_checkpoint -force $outputDir/post_synth.dcp report_timing_summary -file $outputDir/post_synth_timing_summary.rpt report_utilization -file $outputDir/post_synth_util.rpt |