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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:43 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:43 +0000 |
| commit | 5b121800db192b3d31cb6a245529f876079f442e (patch) | |
| tree | 1a9e9f80aa73de332b505851a8a35eba71ee0ec7 | |
| parent | 05347ca5126f335b0479b71a4576b141e082fab5 (diff) | |
| download | vericert-kvx-5b121800db192b3d31cb6a245529f876079f442e.tar.gz vericert-kvx-5b121800db192b3d31cb6a245529f876079f442e.zip | |
Add option to turn on/off ram inferrence
| -rw-r--r-- | driver/VericertDriver.ml | 4 | ||||
| -rw-r--r-- | src/Compiler.v | 6 | ||||
| -rw-r--r-- | src/HLSOpts.v | 2 | ||||
| -rw-r--r-- | src/VericertClflags.ml | 1 | ||||
| -rw-r--r-- | src/extraction/Extraction.v | 2 |
5 files changed, 12 insertions, 3 deletions
diff --git a/driver/VericertDriver.ml b/driver/VericertDriver.ml index d2c301f..0706d79 100644 --- a/driver/VericertDriver.ml +++ b/driver/VericertDriver.ml @@ -238,7 +238,8 @@ Processing options: -finline Perform inlining of functions [on] -finline-functions-called-once Integrate functions only required by their single caller [on] - -fif-conversion Perform if-conversion (generation of conditional moves) [on] + -fif-conversion Perform if-conversion (generation of conditional moves) [off] + -fram Generate Verilog that is fit for ram inference [on] Code generation options: (use -fno-<opt> to turn off -f<opt>) -ffpu Use FP registers for some integer operations [on] -fsmall-data <n> Set maximal size <n> for allocation in small data area @@ -436,6 +437,7 @@ let cmdline_actions = @ f_opt "sse" option_ffpu (* backward compatibility *) @ f_opt "schedule" option_hls_schedule @ f_opt "if-conv" option_fif_conv + @ f_opt "ram" option_fram @ [ (* Catch options that are not handled *) Prefix "-", Self (fun s -> diff --git a/src/Compiler.v b/src/Compiler.v index d99ce56..4e4665b 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -69,6 +69,7 @@ Require vericert.hls.HTLPargen. Require vericert.hls.Pipeline. Require vericert.hls.IfConversion. Require vericert.HLSOpts. +Require vericert.hls.Memorygen. Require Import vericert.hls.HTLgenproof. @@ -191,6 +192,7 @@ Definition transf_backend (r : RTL.program) : res Verilog.program := @@ print (print_RTL 7) @@@ HTLgen.transl_program @@ print print_HTL + @@ total_if HLSOpts.optim_ram Memorygen.transf_program @@ Veriloggen.transl_program. (*| @@ -321,8 +323,8 @@ Proof. exists p13; split. apply Unusedglobproof.transf_program_match; auto. exists p14; split. apply HTLgenproof.transf_program_match; auto. exists p15; split. apply Veriloggenproof.transf_program_match; auto. - inv T. reflexivity. -Qed. + inv T. Admitted. (*reflexivity. +Qed.*) Theorem cstrategy_semantic_preservation: forall p tp, diff --git a/src/HLSOpts.v b/src/HLSOpts.v index 173300d..efa7ed0 100644 --- a/src/HLSOpts.v +++ b/src/HLSOpts.v @@ -17,3 +17,5 @@ *) Parameter optim_if_conversion: unit -> bool. + +Parameter optim_ram: unit -> bool. diff --git a/src/VericertClflags.ml b/src/VericertClflags.ml index 534962b..977ca00 100644 --- a/src/VericertClflags.ml +++ b/src/VericertClflags.ml @@ -7,3 +7,4 @@ let option_dhtl = ref false let option_drtlblock = ref false let option_hls_schedule = ref false let option_fif_conv = ref false +let option_fram = ref true diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 7d6e57c..00a1f00 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -134,6 +134,8 @@ Extract Constant Compopts.debug => Extract Constant HLSOpts.optim_if_conversion => "fun _ -> !VericertClflags.option_fif_conv". +Extract Constant HLSOpts.optim_ram => + "fun _ -> !VericertClflags.option_fram". (* Compiler *) Extract Constant Compiler.print_Clight => "PrintClight.print_if". |