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authorYann Herklotz <git@yannherklotz.com>2021-01-13 17:57:23 +0000
committerYann Herklotz <git@yannherklotz.com>2021-01-13 17:57:23 +0000
commit6cff3d1683ed19ca497975394d9a11df1b027c28 (patch)
tree38c88cacb4da8ca30043a9bf4001607ff12b54bb
parent2f4682ed99595587a08aaf18248dc470efc6472b (diff)
downloadvericert-kvx-6cff3d1683ed19ca497975394d9a11df1b027c28.tar.gz
vericert-kvx-6cff3d1683ed19ca497975394d9a11df1b027c28.zip
Add missing modules to extraction and compile
-rw-r--r--src/Compiler.v6
-rw-r--r--src/extraction/Extraction.v3
2 files changed, 5 insertions, 4 deletions
diff --git a/src/Compiler.v b/src/Compiler.v
index 5895e1d..ce36d5b 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -74,7 +74,8 @@ From vericert Require
HTLgen
RTLBlock
RTLBlockgen
- HTLSchedulegen
+ RTLPargen
+ HTLPargen
Pipeline.
From compcert Require Import Smallstep.
@@ -245,7 +246,8 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program :=
@@ print (print_RTL 8)
@@@ RTLBlockgen.transl_program
@@ print print_RTLBlock
- @@@ HTLSchedulegen.transl_program
+ @@@ RTLPargen.transl_program
+ @@@ HTLPargen.transl_program
@@ print print_HTL
@@ Veriloggen.transl_program.
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v
index 7736bfa..f4f1c26 100644
--- a/src/extraction/Extraction.v
+++ b/src/extraction/Extraction.v
@@ -21,7 +21,6 @@ From vericert Require
Compiler
RTLBlockgen
RTLBlock
- HTLSchedulegen
HTLgen
Pipeline.
@@ -172,7 +171,7 @@ Extract Inlined Constant Bracket.inbetween_loc => "fun _ -> assert false".
Extract Constant Pipeline.pipeline => "SoftwarePipelining.pipeline".
Extract Constant RTLBlockgen.partition => "Partition.partition".
-Extract Constant HTLSchedulegen.transl_module => "Schedule.transl_module".
+Extract Constant RTLPargen.schedule => "Schedule.schedule_fn".
(* Needed in Coq 8.4 to avoid problems with Function definitions. *)
Set Extraction AccessOpaque.