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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-24 12:59:06 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-24 12:59:06 +0100 |
| commit | a6fb1adadcf2421b76cde649369f457a2a9ed66c (patch) | |
| tree | 430f8bf9031e506c2a6452687bc7c0c154c29d20 | |
| parent | 244270b446721d5eeb1ed15ec2839aa4d246965c (diff) | |
| download | vericert-kvx-a6fb1adadcf2421b76cde649369f457a2a9ed66c.tar.gz vericert-kvx-a6fb1adadcf2421b76cde649369f457a2a9ed66c.zip | |
Compile HTLPargen again
| -rw-r--r-- | src/Compiler.v | 4 | ||||
| -rw-r--r-- | src/hls/HTLPargen.v | 7 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index de29889..268f451 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -216,7 +216,7 @@ Definition transf_hls (p : Csyntax.program) : res Verilog.program := (* This is an unverified version of transf_hls with some experimental additions such as scheduling that aren't completed yet. *) -(*Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := +Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := OK p @@@ SimplExpr.transl_program @@@ SimplLocals.transf_program @@ -245,7 +245,7 @@ that aren't completed yet. *) @@@ RTLPargen.transl_program @@@ HTLPargen.transl_program @@ print print_HTL - @@ Veriloggen.transl_program.*) + @@ Veriloggen.transl_program. (*| Correctness Proof diff --git a/src/hls/HTLPargen.v b/src/hls/HTLPargen.v index 40d1dcc..9746f92 100644 --- a/src/hls/HTLPargen.v +++ b/src/hls/HTLPargen.v @@ -641,9 +641,9 @@ Definition add_control_instr_force_state_incr : s.(st_arrdecls) s.(st_datapath) (AssocMap.set n st s.(st_controllogic))). -Abort. +Admitted. -(*Definition add_control_instr_force (n : node) (st : stmnt) : mon unit := +Definition add_control_instr_force (n : node) (st : stmnt) : mon unit := fun s => OK tt (mkstate s.(st_st) @@ -708,7 +708,7 @@ Lemma create_new_state_state_incr: s.(st_arrdecls) s.(st_datapath) s.(st_controllogic)). -Abort. +Admitted. Definition create_new_state (p: node): mon node := fun s => OK s.(st_freshstate) @@ -876,4 +876,3 @@ Definition transl_program (p : RTLBlockInstr.program) : Errors.res HTL.program : if main_is_internal p then transform_partial_program transl_fundef p else Errors.Error (Errors.msg "Main function is not Internal."). -*) |