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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-18 14:40:45 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-18 14:40:45 +0100 |
| commit | b666f88219893c82361606f8652297ecc7fb7a9f (patch) | |
| tree | 946c2ddb5ce21b7af24ce6945fe5f83cbb274061 /src/Compiler.v | |
| parent | c4d44af5f3135aba4d4878f8f41c80d1f0b9e9a2 (diff) | |
| parent | c4436c02648502c4cb327d2018229e62a2c0d1c0 (diff) | |
| download | vericert-kvx-b666f88219893c82361606f8652297ecc7fb7a9f.tar.gz vericert-kvx-b666f88219893c82361606f8652297ecc7fb7a9f.zip | |
Merge branch 'master' into develop
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 61adad1..de29889 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -214,7 +214,9 @@ Definition transf_hls (p : Csyntax.program) : res Verilog.program := .. coq:: none |*) -Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := +(* This is an unverified version of transf_hls with some experimental additions such as scheduling +that aren't completed yet. *) +(*Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := OK p @@@ SimplExpr.transl_program @@@ SimplLocals.transf_program @@ -243,7 +245,7 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@@ RTLPargen.transl_program @@@ HTLPargen.transl_program @@ print print_HTL - @@ Veriloggen.transl_program. + @@ Veriloggen.transl_program.*) (*| Correctness Proof |