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author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
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committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/Compiler.v | |
parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
download | vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/Compiler.v')
-rw-r--r-- | src/Compiler.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index e998521..98ef429 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -74,9 +74,12 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.module := +Definition transf_backend (r : RTL.program) : res Verilog.program := OK r - @@@ Veriloggen.transf_program. + @@@ Inlining.transf_program + @@ print (print_RTL 1) + @@@ HTLgen.transl_program + @@ Veriloggen.transl_program. Definition transf_frontend (p: Csyntax.program) : res RTL.program := OK p @@ -88,7 +91,7 @@ Definition transf_frontend (p: Csyntax.program) : res RTL.program := @@@ RTLgen.transl_program @@ print (print_RTL 0). -Definition transf_hls (p : Csyntax.program) : res Verilog.module := +Definition transf_hls (p : Csyntax.program) : res Verilog.program := OK p @@@ transf_frontend @@@ transf_backend. |