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| author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
| commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
| tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/Simulator.v | |
| parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
| parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
| download | vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip | |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/Simulator.v')
| -rw-r--r-- | src/Simulator.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/Simulator.v b/src/Simulator.v index 930971b..83d3e96 100644 --- a/src/Simulator.v +++ b/src/Simulator.v @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From Coq Require Import FSets.FMapPositive. +(*From Coq Require Import FSets.FMapPositive. From compcert Require Import Errors. @@ -33,3 +33,4 @@ Definition simulate (n : nat) (m : Verilog.module) : res (Value.value * list (po end. Local Close Scope error_monad_scope. +*) |