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author | Yann Herklotz <git@yannherklotz.com> | 2020-08-30 14:03:40 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-08-30 14:03:40 +0100 |
commit | ec319c9ec0acc975fcdfbfa2e378b82c9be9ab0a (patch) | |
tree | aba30758bbbf10ab3d975367f48a695b81afb179 /src/extraction | |
parent | 9d6979baa0e4b505862bcedee1dfd075f36579c3 (diff) | |
download | vericert-kvx-ec319c9ec0acc975fcdfbfa2e378b82c9be9ab0a.tar.gz vericert-kvx-ec319c9ec0acc975fcdfbfa2e378b82c9be9ab0a.zip |
Add RTLBlock intermediate language
Diffstat (limited to 'src/extraction')
-rw-r--r-- | src/extraction/Extraction.v | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index b1a885e..e6ee512 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,11 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From vericert Require Verilog Value Compiler. +From vericert Require + Verilog + Value + Compiler + RTLBlockgen. From Coq Require DecidableClass. @@ -162,12 +166,15 @@ Extract Inlined Constant Binary.B2R => "fun _ -> assert false". Extract Inlined Constant Binary.round_mode => "fun _ -> assert false". Extract Inlined Constant Bracket.inbetween_loc => "fun _ -> assert false". +Extract Constant RTLBlockgen.partition => "Partition.partition". + (* Needed in Coq 8.4 to avoid problems with Function definitions. *) Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction Verilog.module Value.uvalueToZ vericert.Compiler.transf_hls + RTLBlockgen.transl_program Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |