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| author | Yann Herklotz <git@yannherklotz.com> | 2020-11-17 13:14:56 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-11-17 13:14:56 +0000 |
| commit | 2a5b73153060ff9f69403ca81d29c9c9761623d8 (patch) | |
| tree | 089028e9186eb3dc8f2d38f580832d911a807597 /src/hls/HTL.v | |
| parent | 7d9057a6ca6f591851ee5c6e8d74e3833aae3903 (diff) | |
| download | vericert-kvx-2a5b73153060ff9f69403ca81d29c9c9761623d8.tar.gz vericert-kvx-2a5b73153060ff9f69403ca81d29c9c9761623d8.zip | |
Add changes for proof of reset signals with Resetstate
Diffstat (limited to 'src/hls/HTL.v')
| -rw-r--r-- | src/hls/HTL.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/hls/HTL.v b/src/hls/HTL.v index 620ef14..cfc7aa3 100644 --- a/src/hls/HTL.v +++ b/src/hls/HTL.v @@ -120,6 +120,8 @@ Inductive step : genv -> state -> Events.trace -> state -> Prop := ctrl (Verilog.mkassociations basr1 nasr1) (Verilog.mkassociations basa1 nasa1) -> + basr1!(mod_reset m) = Some (ZToValue 0) -> + basr1!(mod_finish m) = Some (ZToValue 0) -> basr1!(m.(mod_st)) = Some (posToValue st) -> Verilog.stmnt_runp f (Verilog.mkassociations basr1 nasr1) |