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author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
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committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/translation/Veriloggenproof.v | |
parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
download | vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/translation/Veriloggenproof.v')
-rw-r--r-- | src/translation/Veriloggenproof.v | 23 |
1 files changed, 4 insertions, 19 deletions
diff --git a/src/translation/Veriloggenproof.v b/src/translation/Veriloggenproof.v index 942a83a..6c58c56 100644 --- a/src/translation/Veriloggenproof.v +++ b/src/translation/Veriloggenproof.v @@ -17,30 +17,15 @@ *) From compcert Require Import Smallstep. -From compcert Require RTL. -From coqup Require Verilog. +From coqup Require HTL Verilog. Section CORRECTNESS. - Variable prog: RTL.program. - Variable tprog: Verilog.module. - - Inductive match_states: RTL.state -> Verilog.state -> Prop := - | match_state: - forall, - - match_states (RTL.State f s k sp e m) - (Verilog.State m mi mis assoc nbassoc f cycle pc) - | match_returnstate: - forall v tv k m tm cs - (MS: match_stacks k cs) - (LD: Val.lessdef v tv) - (MEXT: Mem.extends m tm), - match_states (CminorSel.Returnstate v k m) - (RTL.Returnstate cs tv tm). + Variable prog: HTL.program. + Variable tprog: Verilog.program. Theorem transf_program_correct: - forward_simulation (RTL.semantics prog) (Verilog.semantics tprog). + forward_simulation (HTL.semantics prog) (Verilog.semantics tprog). Admitted. End CORRECTNESS. |