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authorYann Herklotz <git@yannherklotz.com>2020-06-22 10:08:14 +0100
committerYann Herklotz <git@yannherklotz.com>2020-06-22 10:08:14 +0100
commitc5170915a81ca1bca420cd4683855cc7ba8ff8c4 (patch)
tree8c4dc8009cb5ac09b4be976f5c2ec9cd87ad7ec8 /src/verilog/PrintVerilog.mli
parent11ff840afe29c5340582e513613dc70c13879997 (diff)
parent9089af0dbd8dc079c16501c73727df82c34c530d (diff)
downloadvericert-kvx-c5170915a81ca1bca420cd4683855cc7ba8ff8c4.tar.gz
vericert-kvx-c5170915a81ca1bca420cd4683855cc7ba8ff8c4.zip
Merge branch 'master' into develop
Diffstat (limited to 'src/verilog/PrintVerilog.mli')
-rw-r--r--src/verilog/PrintVerilog.mli2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli
index 0df9d06..6544e52 100644
--- a/src/verilog/PrintVerilog.mli
+++ b/src/verilog/PrintVerilog.mli
@@ -18,6 +18,6 @@
val print_value : out_channel -> Value.value -> unit
-val print_program : out_channel -> Verilog.program -> unit
+val print_program : bool -> out_channel -> Verilog.program -> unit
val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit